This document describes techniques, methods, and apparatuses for logical memory repair. In some aspects, a memory built-in self-test (MBIST) controller can perform logical memory repair for a memory cluster including a shared bus interface that is coupled to the MBIST controller and configured to provide access to multiple logical memories. The memory cluster includes multiple physical memories that are coupled to the shared bus interface. At least one physical memory is configured to have two or more logical memories overlaid thereon. In example aspects, the physical memory includes arbitration logic coupled to a first address register and a second address register that are respectively configured to store a first faulty memory address and a second faulty memory address. The arbitration logic includes circuitry configured to arbitrate access to at least one spare memory portion responsive to the first faulty memory address conflicting with the second faulty memory address.

A location of at least one fail bit to be repaired in a memory block of a memory is extracted from at least one memory test on the memory block. An available repair resource in the memory for repairing the memory block is obtained. It is checked, using machine learning, whether the at least one fail bit is unrepairable, according to the location of the at least one fail bit, and the available repair resource. When the checking indicates that the at least one fail bit is not unrepairable, it is determined whether a Constraint Satisfaction Problem (CSP) containing a plurality of constraints is solvable. The constraints correspond to the location of the at least one fail bit in the memory block, and the available repair resource. In response to determining that the CSP is not solvable, the memory block is marked as unrepairable or the memory is rejected.

A method of detecting error in a data plane of a packet forwarding element that includes a plurality of physical ternary content-addressable memories (TCAMs) is provided. The method configures a first set of physical TCAMs into a first logical TCAM. The method configures a second set of physical TCAMs into a second logical TCAM. The second logical TCAM includes the same number of physical TCAMs as the first logical TCAM. The method programs the first and second logical TCAMs to store a same set of data. The method requests a search for a particular content from the first and second logical TCAMs. The method generates an error signal when the first and second logical TCAMs do not produce a same search results.

Apparatuses and methods for repairing memory devices including a plurality of memory die and an interface are disclosed. An example apparatus includes a first stack that includes a plurality of first dies stacked with one another, the first dies include a plurality of first channels, at least one of which is designated as a first defective channel, and further includes a second stack stacked with the first stack and including a plurality of second dies stacked with one another, the second dies including a plurality of second channels, at least one of which is designated as a second defective channel. A control circuit is configured, responsive to a command for accessing the first defective channel, to access one of the plurality of second channels in place of accessing the first defective channel, wherein the one of the plurality of second channels corresponds to the first defective channel and is not designated as the second defective channel.

Apparatuses and methods for repairing memory devices including a plurality of memory die and an interface are disclosed. An example apparatus includes a first stack that includes a plurality of first dies stacked with one another, the first dies include a plurality of first channels, at least one of which is designated as a first defective channel, and further includes a second stack stacked with the first stack and including a plurality of second dies stacked with one another, the second dies including a plurality of second channels, at least one of which is designated as a second defective channel. A control circuit is configured, responsive to a command for accessing the first defective channel, to access one of the plurality of second channels in place of accessing the first defective channel, wherein the one of the plurality of second channels corresponds to the first defective channel and is not designated as the second defective channel.

Various embodiments comprise methods and related apparatuses formed from those methods for placing at least portions of peripheral circuits under a DRAM memory array, where the peripheral circuits are used to control an operation of the DRAM memory array. In an embodiment, a memory apparatus includes a DRAM memory array and at least one peripheral circuit formed under the DRAM memory array, where the at least one peripheral circuit includes at least one circuit type selected from sense amplifiers and sub-word line drivers. Additional apparatuses and methods are also disclosed.

A method for correcting bit defects in an STT-MRAM memory is disclosed. The method comprises executing a read before write operation in the STT-MRAM memory, wherein the STT-MRAM memory comprises a plurality of codewords, wherein each codeword comprises a plurality of redundant bits. The read before write operation comprises reading a codeword and mapping defective bits in the codeword. Further, the method comprises replacing the defective bits in the codeword with a corresponding redundant bit and executing a write operation with corresponding redundant bits in place of the defective bits.

A method for correcting bit defects in a memory array is disclosed. The method comprises determining, during a characterization stage, a resistance distribution for the memory array by classifying a state of each bit-cell in the memory array, wherein the memory array comprises a plurality of codewords, wherein each codeword comprises a plurality of redundant bits. Further, the method comprises determining bit-cells in the resistance distribution that are ambiguous, wherein ambiguous bit-cells have ambiguous resistances between being high or low bits. Subsequently, the method comprises forcing the ambiguous bit-cells to short circuits and replacing each short-circuited ambiguous bit-cell with a corresponding redundant bit from an associated codeword.

Techniques are disclosed for achieving size reduction of embedded memory arrays through determining a spare-core layout. In an embodiment, input parameters comprising global process parameters are combined with design characteristics to compute yield values corresponding to potential redundancy configurations for a die. Resulting yields may be compared to determine which redundancy configuration is suitable to maintain a particular yield. A die configured with one or more spare cores (with no redundant memory therein) results in a yield which is equivalent to, or exceeds, the yield of a die with conventional memory redundancies. In some example cases, memory redundancy is eliminated from cores. Another embodiment provides a semiconductor structure having including an array of redundant cores, each including a composition of memory arrays and logic structures, wherein at least one of the memory arrays of each redundant core is implemented without at least one of row redundancy and column redundancy.

A stack of vertically-connected, horizontally-oriented integrated circuits (ICs) may have electrical connections from the front side of one IC to the back side of another IC. Electrical signals may be transferred from the back side of one IC to the front side of the same IC by means of through substrate vias (TSVs), which may include through silicon vias. Electronic apparatus, systems, and methods may operate to test and/or replace defective TSVs. Additional apparatus, systems and methods are disclosed.