A redundancy circuit includes a selection control signal generation circuit and a column control circuit. The selection control signal generation circuit drives an internal node, which is initialized, to generate a selection control signal when a logic level of a latched address signal is different from a logic level of a fuse signal. The column control circuit buffers a pre-column selection signal based on the selection control signal to generate a column selection signal for execution of a column operation of cells or to generate a redundancy column selection signal for execution of the column operation of redundancy cells.

In an example, a method of memory repair may include receiving, by a memory repair unit, a plurality of memory identifiers. The method may include determining, by the memory repair unit, that a first memory identifier of the plurality of memory identifiers corresponds to a first memory of a plurality of memories. The method may include determining, by the memory repair unit, that a second memory identifier corresponds to a second memory of the plurality of memories. The method may include outputting, by the memory repair unit, in parallel: a first value to a repair enable input of the first memory, and a second value to a repair enable input of the second memory.

System and method of read deskew training for 4 mode memory control interface configurations. A read deskew training process includes aligning the two strobe signals serving one byte before deskewing the data bits against their corresponding strobe signals. A deskew setting of a variable delay line associated with the second strobe signal is adjusted to align the second strobe signal with reference to the first strobe signal. By aligning the two strobe signals with respect to each other, the read leveling settings can be common within the byte even the two DQS signals are transmitted to or received from two different memory storage devices.

System and method of write deskew training for 4 mode memory control interface configurations. Write leveling logic in the memory controller is adjusted to obtain a write leveling setting for delaying both first and second strobe signals associated with a byte. The adjustment is based on feedback of first set of bits of a byte and irrespective of the feedback of the second set of bits of the byte. The write leveling logic is then anchored at the write leveling setting, and a deskew delay line for the second strobe signal is adjusted to obtain a first deskew setting based on the feedback of the second set of bits. Thus, in write operations, the write leveling setting can be common within the byte even the two strobe signals are transmitted to or received from two different memory storage devices.

An address control circuit may be provided. The address control circuit may include a first path circuit configured to generate a block select signal according to a control signal and an address signal. The address control circuit may include a second path circuit configured to generate, using the control signal, a dummy address signal making a transition at a timing substantially identical with a transition timing of the address signal, and generate, using the dummy address signal, an address latch signal for latching the block select signal.

An address control circuit may be provided. The address control circuit may include a first path circuit configured to generate a block select signal according to a control signal and an address signal. The address control circuit may include a second path circuit configured to generate, using the control signal, a dummy address signal making a transition at a timing substantially identical with a transition timing of the address signal, and generate, using the dummy address signal, an address latch signal for latching the block select signal.

An address control circuit may be provided. The address control circuit may include a first path circuit configured to generate a block select signal according to a control signal and an address signal. The address control circuit may include a second path circuit configured to generate, using the control signal, a dummy address signal making a transition at a timing substantially identical with a transition timing of the address signal, and generate, using the dummy address signal, an address latch signal for latching the block select signal.

In an example, a method of memory repair may include receiving, by a memory repair unit, a plurality of memory identifiers. The method may include determining, by the memory repair unit, that a first memory identifier of the plurality of memory identifiers corresponds to a first memory of a plurality of memories. The method may include determining, by the memory repair unit, that a second memory identifier corresponds to a second memory of the plurality of memories. The method may include outputting, by the memory repair unit, in parallel: a first value to a repair enable input of the first memory, and a second value to a repair enable input of the second memory.

An address control circuit may be provided. The address control circuit may include a first path circuit configured to generate a block select signal according to a control signal and an address signal. The address control circuit may include a second path circuit configured to generate, using the control signal, a dummy address signal making a transition at a timing substantially identical with a transition timing of the address signal, and generate, using the dummy address signal, an address latch signal for latching the block select signal.

An address generation device of a memory system includes an address generator and a synchronizer. The address generator may receive a clock and sequentially generate a first address and a second address after the first address. The synchronizer may synchronize the first address in response to the clock at a preset time point before the second address is generated by the address generator, and output the synchronized address as an output address.