Provided are a memory device and a memory module, which perform both an ECC operation and a redundancy repair operation. The memory device repairs a single-bit error due to a fail cell by using an error correction code (ECC) operation, and also repairs the fail cell by using a redundancy repair operation when the fail cell is not repairable by the ECC operation. The redundancy repair operation includes a data line repair and a block repair. The ECC operation may change a codeword corresponding to data per one unit of memory cells including the fail cell, and may also change the size of parity bits regarding the changed codeword.

A three-dimensional stacked integrated circuit (3D SIC) having a non-volatile memory die, a volatile memory die, and a logic die. The non-volatile memory die, the volatile memory die, and the logic die are stacked. The 3D SIC is partitioned into a plurality of columns that are perpendicular to each of the stacked dies. Each column of the plurality of columns is configurable to be bypassed via configurable routes. When the configurable routes are used, functionality of a failing part of the column is re-routed to a corresponding effective part of a neighboring column.

A memory device including a first configuration bit group including a plurality of bits, the plurality of bits including: a plurality of configuration bits; at least one redundant configuration bit; a plurality of configuration bit multiplexers each configured to receive (i) a first input from a first bit in the plurality of bits and/or a second input from a second bit in the plurality of bits and (ii) a third input from a decoder, each of the first, second, and third inputs indicating a respective logical state, wherein the logical state includes a first state or a second state; and wherein, based on the logical state of the third input received from the decoder, each configuration bit multiplexer is configured to output: the logical state of the first input from the first bit, or the logical state of the second input from the second bit.

Provided is a memory device including a memory cell array including a normal area in which a plurality of memory cells are arranged, and a redundancy area in which a plurality of redundancy memory cells are arranged, and a repair controller configured to control a repair operation on a defect cell from among the plurality of memory cells according to a first repair unit, and switch a repair unit from the first repair unit to a second repair unit different from the first repair unit when the repair operation based on the first repair unit is completed.

In certain aspects, a memory device includes an array of memory cells, an input/output (I/O) circuit, and I/O control logic coupled to the I/O circuit. The array of memory cells includes P groups of banks. Each group of banks includes N main banks and M redundant banks, where each of P, N and M is a positive integer, and N is greater than M. The I/O circuit is coupled to the P groups of banks and configured to direct PN pieces of data to or from PN working banks, respectively. One of the M redundant banks is coupled with at least two main banks of the N main banks through the I/O circuit. The I/O control logic is configured to in responding to K main banks of the P groups of banks failed, determine the PN working banks including K redundant banks of PM redundant banks, where K is a positive integer not greater than P, and control the I/O circuit to direct PN pieces of data to or from the PN working banks, respectively.

Provided is a memory device including a memory cell array including a normal area in which a plurality of memory cells are arranged, and a redundancy area in which a plurality of redundancy memory cells are arranged, and a repair controller configured to control a repair operation on a defect cell from among the plurality of memory cells according to a first repair unit, and switch a repair unit from the first repair unit to a second repair unit different from the first repair unit when the repair operation based on the first repair unit is completed.

Provided are a memory device and a memory module, which perform both an ECC operation and a redundancy repair operation. The memory device repairs a single-bit error due to a fail cell by using an error correction code (ECC) operation, and also repairs the fail cell by using a redundancy repair operation when the fail cell is not repairable by the ECC operation. The redundancy repair operation includes a data line repair and a block repair. The ECC operation may change a codeword corresponding to data per one unit of memory cells including the fail cell, and may also change the size of parity bits regarding the changed codeword.

Provided are a memory device and a memory module, which perform both an ECC operation and a redundancy repair operation. The memory device repairs a single-bit error due to a fail cell by using an error correction code (ECC) operation, and also repairs the fail cell by using a redundancy repair operation when the fail cell is not repairable by the ECC operation. The redundancy repair operation includes a data line repair and a block repair. The ECC operation may change a codeword corresponding to data per one unit of memory cells including the fail cell, and may also change the size of parity bits regarding the changed codeword.

Various implementations described herein are directed to a device having a bank of bitcells split into a plurality of portions including a first row slice of the bitcells and a second row slice of the bitcells. Also, the device may have control circuitry configured to access and repair a first bitcell in the first row slice with a first row address and a second bitcell in the second row slice with a second row address that is different than the first row address.

A system includes a memory block. The memory block includes a local control circuit that is operable to control a memory operation of the memory block. The local control circuit includes a local sense amplifier. The system also includes a global memory control circuit separate from the memory block, and the global memory control circuit is operable to communicate with the local control circuit. The global memory control circuit includes a global data latch operable to receive a sensed data state from the local sense amplifier.