There is provided a system and method of examination of a semiconductor specimen using an examination recipe. The method includes obtaining a registered image pair, for each design-based structural element associated with a given layer, calculating an edge attribute, using a trained classifier to determine a class of the design-based structural element, and generating a layer score usable to determine validity of the registered image pair. There is also provided a system and method of generating the examination recipe usable for examination of a semiconductor specimen.

In an embodiment, a system includes: an orientation sensor configured to detect an orientation fiducial on a bevel of a wafer; a pedestal configured to rotate the wafer to allow the orientation sensor to detect the orientation fiducial and place the orientation fiducial at a predetermined orientation position; and a defect sensor configured to detect a wafer defect along a surface of the wafer while rotated by the pedestal.

In a device for observing a semiconductor wafer, a positional relationship between an in-wafer region and a background region in an imaging field of view is not constant when an outer peripheral portion of the wafer is imaged, which results in an increase in the quantity of calculation in defect detection and image classification processing and makes it difficult to efficiently perform defect observation and analysis. There is provided a defect observation system for a semiconductor wafer, and the system includes: a stage on which the semiconductor wafer is placed and which is movable in an XY direction, an imaging unit that is configured to image a portion including an edge of the semiconductor wafer, and an image output unit that is configured to, with respect to a plurality of images obtained by imaging, output images in which edges of the wafer are substantially in parallel among the plurality of images.

One illustrative system includes a processor and memory storing instructions that, when executed by the processor, cause the system to receive a device layout including a curvilinear feature, define a plurality of vertices for the curvilinear feature, determine a radius of curvature between a selected vertex in the plurality of vertices and a neighboring vertex in the plurality of vertices, and identify a design rule violation for the curvilinear feature responsive to the radius of curvature being less than a predetermined threshold.

A method of monitoring a semiconductor process includes the following steps. A process parameter is set to a first condition. A first process is performed to form a first film layer on a first wafer. The first film layer does not cover a wafer edge region of the first wafer. The first wafer having the first film layer is photographed by an image capturing device to obtain a first wafer image. Image recognition is performed to the first wafer image to obtain first data. Whether a position of the first film layer is offset is determined according to the first data.

One illustrative system includes a processor and memory storing instructions that, when executed by the processor, cause the system to receive a device layout including a curvilinear feature, define a plurality of vertices for the curvilinear feature, determine a radius of curvature between a selected vertex in the plurality of vertices and a neighboring vertex in the plurality of vertices, and identify a design rule violation for the curvilinear feature responsive to the radius of curvature being less than a predetermined threshold.

A three-dimensional calibration structure for measuring buried defects on a semiconductor device is disclosed. The three-dimensional calibration structure includes a defect standard wafer (DSW) including one or more programmed surface defects. The three-dimensional calibration structure includes a planarized layer deposited on the DSW. The three-dimensional calibration structure includes a layer stack deposited on the planarized layer. The layer stack includes two or more alternating layers. The three-dimensional calibration structure includes a cap layer deposited on the layer stack. One or more air gaps are formed in the layer stack following deposition of the cap layer. The three-dimensional calibration structure includes one or more holes formed into at least one of the cap layer, the layer stack, or the planarized layer.

A system, computer program product and a method for detecting manufacturing process defects, the method may include: obtaining multiple edge measurements of one or more structural elements after a completion of each one of multiple manufacturing phases; generating spatial spectrums, based on the multiple edge measurements, for each one of the multiple manufacturing phases; determining relationships between bands of the spatial spectrums; and identifying at least one of the manufacturing process defects based on the relationships between the bands of the spatial spectrums.

A semiconductor device manufacturing system includes a spin coater and a coating layer inspector. The spin coater includes: a chuck, a rotation driver configured to rotate the chuck; and a solution dispenser configured to spray a solution onto a portion of the coating layer formed on an edge portion of the wafer, wherein the coating layer inspector includes an edge inspection camera and an inspection controller configured to determine a radius, eccentricity, and a top-view shape of the coating layer, based on images of the edge portion of the wafer.

A first light source is directed at an outer surface of a workpiece in an inspection module. The light from the first light source that is reflected from the outer surface of the workpiece is directed to the camera via a first pathway. The light from the first light source transmitted through the workpiece is directed to the camera via a second pathway. A second light source is directed at the outer surface of the workpiece 180 from that of the first light source. The light from the second light source that is reflected from the outer surface of the workpiece is directed to the camera via the second pathway. The light from the second light source transmitted through the workpiece is directed to the camera via the first pathway.