Methods and systems for authenticating electronic devices via multi tone analysis. A method for authenticating a device under test (DUT) of a type of DUT includes imparting voltage tones to the DUT. The voltage tones are proximate a frequency of interest that is associated with the type of DUT. Using a measurement response of the DUT to the voltage tones, an electronic signature of the DUT is determined. The DUT is determined to be authentic when the electronic signature of the DUT substantially matches an electronic signature of an authority DUT of the type of DUT.

Spike safe floating current and voltage source (VI) containing a forced voltage amplifier in series with a selectable resistor. A method of providing a VI with forced current testing mode using a forced voltage amplifier in series with a selectable resistor. A method of providing a VI with forced voltage testing mode using a forced voltage amplifier in series with a selectable resistor. A method of measuring the on resistance of a device under test using a VI with a forced voltage amplifier in series with a selectable resistor. A method of measuring the breakdown of an input/output junction of a device under test using a VI with a forced voltage amplifier in series with a selectable resistor.

A signal generating device for generation of measurement signals for an electrical system includes a housing which features an electrically conducting material, an energy reservoir arranged in the housing, a data interface arranged at the housing and designed to receive signal data, a coupling interface arranged at the housing and coupled to the electrical system, and a signal generator arranged in the housing. The signal generator is coupled to the electrical energy reservoir, to the data interface and to the coupling interface. The signal generator is designed, based on the signal data, to generate the measurement signals and to output them via the coupling interface. A corresponding measuring device is also included.

A display device includes a substrate, one line on the substrate, the one line extending from a peripheral region through a display region, pixels on the display region, the pixels being connected to the one line, an outer line on the peripheral region, the outer line being connected to the one line during a short circuit test process that detects a position of a short circuit defect, an electrostatic protection resistor on the peripheral region, the electrostatic protection resistor being connected to the outer line, a pad on the peripheral region, the pad being connected to the outer line through the electrostatic protection resistor, a short circuit test signal being applied to the pad during the short circuit test process, and a bypass line connecting a node between the pad and the electrostatic protection resistor to the outer line.

A test apparatus includes a tray including at least a first region and a second region, and a cap disposed over the tray. The cap includes a cap body, and at least a first magnet and a second magnet disposed over the cap body. The first magnet is configured to provide a first magnetic field to the first region of the tray, and the second magnet is configured to provide a second magnetic field to the second region of the tray. A strength of the first magnetic field is different from a strength of the second magnetic field.

According to one embodiment, an electronic circuit includes: a current supply circuit, a detection circuit, a timing generation circuit, a sample hold circuit and a calculation circuit. The current supply circuit supplies a sine wave current for measurement to a gate terminal of a semiconductor switching device. The detection circuit detects a sine wave voltage generated in response to supply of the sine wave current to generate a detection signal. The timing generation circuit counts cycles of the sine wave voltage. The sample hold circuit samples the detection signal at a timing depending on a count value of the timing generation circuit. The calculation circuit calculates a gate resistance of the semiconductor switching device based on the sampled voltage.

A device and a method for testing receptacle wiring are revealed. The device for testing receptacle wiring includes a signal transmitter and a receiver. The signal transmitted is plugged into a receptacle to be tested while the receiver is used to detect voltage signals of no-fuse breakers (NFB) and receive signals from the signal transmitter so as to find out correspondence between the NFB and the receptacle correctly.

A cloud-based signal generator system is described. The signal generator system includes a server being connectable to at least one client via a computer communication network. The server includes a waveform definition module. The waveform definition module is configured to receive a user request. The waveform definition module further is configured to process the user request and to generate at least one signal parameter that is associated with a custom waveform based on the user request. The server further includes a waveform verification module. The waveform verification module is configured to analyze the custom waveform based on the at least one signal parameter, thereby generating waveform analysis data. The waveform verification module is configured to forward the waveform analysis data to the at least one client. Further, a method for providing a signal including a custom waveform is described.

Systems and methods are described herein for charge-based capacitor measurement. The system includes a first pseudo-inverter circuit and a second pseudo-inverter circuit. The system also includes a control circuit coupled between the first inverter circuit and the second inverter circuit. The control circuit is configured to generate independent and non-overlapping control signals for the first pseudo-inverter circuit and the second pseudo-inverter circuit. A shielding metal is coupled to the first pseudo-inverter circuit, the second pseudo-inverter circuit, and the control circuit. The shielding metal is configured to dissipate parasitic capacitance of at least one of the first pseudo-inverter circuit or the second pseudo-inverter circuit. A device under test is coupled to each of the first inverter circuit and the second inverter circuit.

Boundary test circuit, memory and boundary test method are provided. The boundary test circuit may include a plurality of serially-connected wrapper boundary registers (WBRs) and a plurality of toggle circuits (TCs). Each WBR may include a first I/O for receiving an initial test signal and a second I/O for transmitting the initial test signal to the WBR at a succeeding stage. Each TC may include an input for receiving the initial test signal stored in a corresponding WBR, a control I/O for receiving a toggle signal, and an output for transmitting a real-time test signal to the integrated circuit. The toggle signal may be configured to control phase switching of the real-time test signal, and, depending on the toggle signal, the real-time test signal may have a phase identical or inverse to a phase of the initial test signal. This method improves the efficiency and flexibility of the boundary test.