A self-heating effect apparatus includes a memory and a processor. The processor is coupled to the memory and configured to process a self-heating effect model for characterizing a heat flow network of devices. The devices include a device under test and one or more adjacent devices surrounding the device under test. The self-heating effect model includes a reference thermal resistance and a reference thermal capacity; a thermal temperature feedback model used to acquire a thermal level of the device under test; a thermal resistance modification model used to acquire a modified thermal resistance of the device under test according to the thermal level of the device under test and the reference thermal resistance; and a thermal capacity modification model used to acquire a modified thermal capacity of the device under test according to the thermal level of the device under test and the reference thermal capacity.

A test vehicle, along with methods for fabricating and using a test vehicle, are disclosed herein. In one example, a test vehicle is provided that includes a substrate, at least a first passive die mounted on the substrate, and at least a first test die mounted on the substrate. The first test die includes test circuitry configured to test continuity through solder interconnects formed between the substrate and the first passive die.

A method for detecting non-convergence error in a transient circuit simulation wherein a circuit netlist and control statements associated with a circuit for the transient circuit simulation are received. A transient circuit simulation is performed responsive to a time point. Whether a non-convergence error has occurred during transient circuit simulation is determined. A transient debug mode is actuated responsive to determination of occurrence of the non-convergence error. The steps of performing the transient circuit simulation and determining whether a non-convergence error has occurred are repeated after actuation of the transient debug mode. Results of the transient circuit simulation are provided responsive to a determination of non-occurrence of a non-convergence error.

A testing structure is disclosed. The testing structure includes a first layer, a second layer, and a third layer. The first layer includes a first pattern. The third layer includes a second pattern. The first layer, the second layer, and the third layer overlap each other. The second layer is connected to a CBCM (charged based capacitance measurement) testing circuit.

A DC/DC converter fault diagnosis method based on an improved sparrow search algorithm, includes: establishing an simulation module of the converter, selecting a leakage inductance current of a transformer as a diagnosis signal, and collecting diagnosis signal samples under OC faults of different power switching devices of the converter as a sample set; improving a global search ability of a sparrow search algorithm by using a Levy flight strategy; dividing the sample set into a training set and a test set, preliminarily establishing an architecture of a deep belief network, and initializing network parameters; optimizing a quantity of hidden-layer units of the deep belief network by using an improved sparrow search algorithm, to obtain a best quantity of hidden-layer units of the deep belief network; and training an optimized deep belief network obtained based on the improved sparrow search algorithm, and obtaining a fault diagnosis result based on a trained network.

The present disclosure discloses a glitch occurring point detection method to detect at least one glitch occurring point in an under-test circuit that includes the steps outlined below. An IC design file is retrieved to further retrieve a plurality of input nodes, at least one output node and a plurality of power nodes corresponding to the under-test circuit in the IC design file. Signals are fed to the input nodes and the power nodes such that a DC analysis is performed on a plurality of internal circuit nodes in the under-test circuit and a plurality of candidate floating points that do not have any charging or discharging path connected thereto are retrieved according to the DC analysis. Each of the candidate floating points capable of triggering the output node during the operation of the under-test circuit are determined to be the glitch occurring point.

The present invention relates to an apparatus for calibrating a battery simulator having an input and an output, wherein a current path with an apparatus for measuring the current strength and with at least one capacitor is provided between the input and output. Furthermore, a voltage path can be provided between the input and output, with an apparatus for measuring the voltage and/or a current transformer, in the secondary current of which the apparatus for measuring the current strength is connected. If a battery simulator is connected to the apparatus it can charge the capacitor and then the capacitor can charge the battery simulator, whilst the current strength and voltage are measured, and on that basis the internal measurement devices of the battery simulator are calibrated.

An improved package device simulator for the testing of testing sockets, the package device simulator being formed of a first layer of non-conductive rigid substrate with a second layer formed of a plurality of electrically conductive traces being added thereto. A third layer of non-conductive rigid substrate is adhered to the first layer with the second layer being sealed there between. The third layer having a plurality of openings therein, wherein the openings align with and expose a portion of the electrically conductive traces of the second layer. Conductive binding material and contact balls are added to the openings and the chip is cured thereby fusing the contact balls with the exposed portions of the traces. Next, the exposed surfaces are coated with a hardening conductive material, such as layers of Nickel and/or Gold. In this way an improved package device simulator is formed that is durable, easier to manufacture and less expensive than a solid metallic package device simulator.

A control and monitoring module is provided for activating an actuator assigned to the control and monitoring module and for monitoring a signal line and/or a power supply line connected to the control and monitoring module and/or to the actuator. The control and monitoring module is configured to detect a fault in the signal line and/or the power supply line, if, during a simulation executed by a testing device, an actual voltage at the control and monitoring module and/or the actuator exceeds a specified upper voltage threshold value or drops below a specified lower voltage threshold value. A system including the control and monitoring module and a method for operating a control and monitoring module are also provided.

A system for simulating reliability of a circuit design includes: a first memory device, arranged to store a technology file, wherein the circuit design comprises a plurality of circuit cells, and the first memory device further stores a plurality of first failure rates corresponding to a first circuit cell in the plurality of circuit cells; a first simulating device, coupled to the first memory device, for generating a first specific failure rate of the first circuit cell according to the plurality of first failure rates and the technology file; and an operating device, coupled to the first simulating device, for generating a total failure rate of the circuit design according to the first specific failure rate.