In a method of manufacturing an integrated circuit involving performing an electrostatic discharge (ESD) test, a weak frequency band is detected by sequentially radiating a plurality of first electromagnetic waves on a first test board including the integrated circuit. First peak-to-peak voltage signals are detected by sequentially radiating the plurality of first electromagnetic waves on a second test board including an electromagnetic wave receiving module. A frequency spectrum is detected by radiating a second electromagnetic wave on a housing including a third test board including the electromagnetic wave receiving module. A second peak-to-peak voltage signal is generated based on the weak frequency band, the first peak-to-peak voltage signals and the frequency spectrum. An ESD characteristic associated with an electronic system including the integrated circuit is predicted based on the second peak-to-peak voltage signal.

A calibration method includes transmitting first data comprising a calibration data and a first checksum to the storage device according to each of a plurality of training parameter sets; recording a plurality of error indicators respectively which are corresponding to the plurality of training parameter sets and from the storage device; and identifying one of the plurality of training parameter sets as a predetermined parameter set according to the plurality of error indicators respectively corresponding to the plurality of training parameter sets; wherein each error indicator indicates whether transmitting the first data according to the corresponded training parameter set is successful.

The probe assembly operates with a circuit board test apparatus and includes a main test probe and a secondary test probes. The probe assembly is capable of moving in X, Y and Z directions relative to a circuit board being tested (UUT). The two test probes are movable linearly relative to each other and rotatable together so as to accurately locate the two probes on selected pins on the UUT, for receiving signals from the selected pins, The received signals are transmitted to a display apparatus.

The present disclosure provides an electronic tester comprising at least one test fixture that couples to a device under test, at least one test instrument coupled to at least one of the test fixtures that measures signals in the device under test, a test controller that controls the device under test while the test is performed, and an adapter module comprising a general control interface that is coupled to the test controller, and a DUT-specific communication interface that couples to the device under test to communicate with the device under test, wherein the test controller controls the device under test with generic control signals sent to the general control interface, and wherein the adapter module translates the general control signals into DUT-specific control signals and transmit the DUT-specific control signals to the device under test. Further, the present disclosure provides a respective method.

An apparatus is described for burn-in and/or functional testing of microelectronic circuits of unsingulated wafers. A large number of power, ground, and signal connections can be made to a large number of contacts on a wafer. The apparatus has a cartridge that allows for fanning-in of electric paths. A distribution board has a plurality of interfaces that are strategically positioned to provide a dense configuration. The interfaces are connected through flexible attachments to an array of first connector modules. Each one of the first connector modules can be independently connected to a respective one of a plurality of second connector modules, thereby reducing stresses on a frame of the apparatus. Further features include for example a piston that allows for tight control of forces exerted by terminals onto contacts of a wafer.

A test system for a memory device includes: a chamber including at least one test socket column having a plurality of test sockets arranged in a first direction, wherein memory devices to be tested are in respective ones of the plurality of test sockets, a temperature adjusting apparatus configured to supply air into the chamber according to a temperature control signal to control a temperature of the chamber, a test device electrically connected to the test sockets and configured to test the memory devices, and a temperature controller configured to receive temperature information of the memory devices from temperature sensors of the memory devices and to output to the temperature adjusting apparatus the temperature control signal to compensate for a temperature difference between a detected temperature of the memory devices and a target temperature.

A system can include a plurality of device under test (DUT) cells. Each DUT cell can include a DUT and a plurality of switches configured to control a flow of current to the DUT. The system can further include a controller configured to execute a plurality of test to the plurality of DUTs in the plurality of DUT cells. Each of the plurality of tests comprises applying a measurement condition to a given DUT of the plurality of DUTs and concurrently applying a stress condition to the remaining DUTs of the plurality of DUTs, wherein the plurality of tests can provide measurements sufficient to determine a bias thermal instability and a time dependent dielectric breakdown of the given DUT.

A system for monitoring and controlling an IC testing machine includes a vibration sensor, a sensor interface, and a processor coupled to the sensor interface. The vibration sensor is in mechanical communication with an IC testing machine to develop an electrical vibration signal representing mechanical vibrations generated by the operation of the IC testing machine. The sensor interface processes the vibration signal to develop vibration data that can be processed by the processor to determine whether the vibration data is indicative of an operational anomaly and, if so, to generate a machine control signal to correct an operation of the IC testing machine. Multiple vibration sensors can be used to increase the amount of vibration data available for analysis.

A wafer inspection device 10 is provided with a chuck top 20 on which a wafer W having semiconductor devices formed thereon is placed, a probe card 18 having multiple contact probes 28 protruding toward the wafer W, a pogo frame 23 for holding the probe card 18, a cylindrical internal bellows 26 configured to suspend from the pogo frame 23 to surround the contact probes 28, and a cylindrical external bellows 27 configured to suspend from the pogo frame 23 to surround the internal bellows 26. When the chuck top 20 approaches the probe card 18 and the contact probes 28 are brought into contact with the devices, the internal bellows 26 and the external bellows 27 come in contact with the chuck top 20, a sealing space P is formed between the internal bellows 26 and the external bellows 27, and the sealing space P is compressed.

A testing system includes: an inspection module including a plurality of levels of inspection chambers in each of which a tester part having a tester configured to perform an electrical inspection of an inspection object and a probe card is accommodated; an aligner module configured to align the inspection object with the tester part; an alignment area in which the aligner module is accommodated; and a loader part configured to load the inspection object into the alignment area and unload the inspection object out of the aligner module, wherein the inspection module is located adjacent to the alignment area.