A system-on-chip includes a clock generation circuit configured to generate a reference clock of a first phase; a transmission circuit comprising a serializer configured to serialize data according to the reference clock of the first phase; a reception circuit comprising a clock data recovery (CDR) circuit configured to receive the serialized data and generate a first recovery clock and recovery data; and a Built In Self Test (BIST) circuit including a CDR performance monitoring circuit configured to generate a control signal provided to a delay controller configured to delay a clock signal by a preset phase difference, and the delay controller configured to delay the clock signal in response to the control signal by the preset phase difference and provide the delayed clock signal to the transmission circuit.

An electronic device includes a control signal generation circuit configured to generate a stress enable signal to enter a stress process and a measurement enable signal to enter a measurement process based on a voltage control signal and configured to generate a cycle signal enable signal for generating a cycle signal, and a cycle signal generation circuit configured to apply stress to a plurality of transistors by supplying the plurality of transistors with a source voltage and a ground voltage when the stress enable signal is activated during the stress process, configured to connect current paths of the plurality of transistors to which the stress is applied when the measurement enable signal is activated during the measurement process, and configured to generate the cycle signal that is cyclically toggled when the cycle signal enable signal is activated.