Systems and methods are provided for generating test patterns. In various embodiments, systems and methods are provided in which machine learning is utilized to generate the test patterns in a manner so that the test patterns conform with design rule check (DRC) specified for a particular semiconductor manufacturing process or for particular types of devices. A test pattern generation system includes test pattern generation circuitry which receives a noise image. The test pattern generation generates a pattern image based on the noise image, and further generates a test pattern based on the pattern image. The test pattern is representative of geometric shapes of an electronic device design layout that is free of design rule check violations.

Aspects of the disclosed technology relate to techniques of test pattern generation based on the cell transition fault model. An assignment for two consecutive clock cycles at inputs of a complex cell in a circuit design is determined based on a gate-level representation of the circuit design. The assignment includes a first transition at one of the inputs which is sensitized by remaining part of the assignment to cause a second transition at an output of the complex cell. A test pattern that generates the assignment at the inputs and propagates a value at the output corresponding to the second clock cycle of the two consecutive clock cycles from the output to an observation point is then derived based on the gate-level representation.

A computer implemented method, and an apparatus, are provided for performing a scalability check on a Hardware Description Language (HDL) representation of a circuit. The HDL representation identifies a plurality of sink signals, where each sink signal is arranged to take a result value computed by performing an operation using as input one or more driver signals. The method comprises creating within a storage a mapping table to map drivers signals to sink signals, where each entry identifies a sink signal and an associated sink width indication, identifies each driver signal used in the computation of the result value for that sink signal along with an associated driver width indication for each driver signal, and an operation type indication for the operation used to compute the result value for the sink signal. A scalability check operation is then executed on processing circuitry for one or more selected entries in the mapping table that have at least one of the sink and driver width indications specified with reference to at least one parameter. The scalability check operation comprises determining, using the operation type indication and the driver width indication for each driver signal, a driver signal identifying an expected width for the sink signal, and determining using the sink width indication a sink formula to identify the width of the sink signal. The sink formula and the driver formula are then evaluated to determine whether the presence of the at least one parameter gives rise to a scalability issue. A result file is then output identifying each sink signal that has been detected to have a scalability issue.

A method of enabling a simulation of a circuit design is described. The method comprises generating, using a computer, an initial representation of the circuit design; simulating the circuit design using the initial representation by driving input signals to the circuit design based upon a simulation event listing; capturing event data associated with a plurality of timestamps in a first file while simulating the circuit design; identifying a plurality of events associated with a timestamp of a plurality of timestamps; reordering events of the plurality of associated with the timestamp; and generating a replay module used to drives input signals to the circuit design. A system for enabling a simulation of a circuit design is also described.

A method and apparatus of validating a test pattern for at-speed testing of at least one integrated circuit, IC, design. The method comprises calculating at least one weighted rise activity, WRA, value for at least one region of the IC design based at least partly on rising gate transitions within the at least one region of the IC design when the test pattern is applied thereto, calculating at least one weighted fall activity, WFA, value for the at least one region of the IC design based at least partly on fall gate transitions within the at least one region of the IC design when the test pattern is applied thereto, and validating the test pattern based at least partly on the WRA value and the WFA value.

Information is received describing test response signals generated by scan cells of an integrated circuit and physical shift failures representing mismatches between the test response signals and expected test response signals of the integrated circuit. The test response signals are mapped to a subset of the scan cells associated with the physical shift failures. Fault simulation is performed for the mapped subset of the scan cells to identify physical faults located within the integrated circuit causing the physical shift failures.

Systems and methods for circuit fault diagnosis are provided. An original circuit design is evaluated to determine whether the original circuit design is to be modified based at least in part on one or more first faults. In response to the original circuit design being determined not to be modified based at least in part on the one or more first faults, a first test pattern set is automatically generated based at least in part on the original circuit design. The original circuit design is evaluated to determine whether the original circuit design is to be modified based at least in part on the first test pattern set. In response to the original circuit design being determined not to be modified based at least in part on the first test pattern set, fault testing is performed to determine whether the original circuit design fails.

Systems and methods disclosed herein provide for automatically diagnosing mis-compares detected during simulation of Automatic Test Pattern Generation (ATPG) generated test patterns. Embodiments of the systems and methods provide for determining the origin of a mis-compare based on an analysis of the generated test patterns with a structural simulator and a behavioral simulator.

This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.

Disclosed here is a system which uses simulations of an electronic circuit and a classifier to create an optimized Test Program Set. A user provides a model of the circuit, including descriptions of common faults. Candidate test signals are simulated in the circuit, evaluated using a classifier and a fitness function which optimizes for fault detection and isolation, and evolved according to a genetic algorithm. The system records the best test signals and terminates after reaching a certain fitness, or after a certain time. The process generates necessary information for an optimized Test Program Set for a given Unit Under Test circuit. This allows test program sets to be generated for complex circuits in a largely automated manner.