This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.

A Design-for-testability method based on composition of test patterns copes with increasing test complexity and cost metric of a large system. System-level structural test patterns from test patterns of constituent subsystems, cores and design IPs are constructed without requiring their design netlists. The delivered test patterns can be utilized 100% in the testing of system. The system-level test pattern is delivered to the device under test, the subsystem test patterns can be scheduled and applied continuously without being interleaved by test deliveries until all of the subsystem test patterns are exercised. Absence of design netlist requirement allows uniform integration of external and internal IPs regardless of availability of test isolation logic or design details. Concurrent test of constituents and their mutual independence in scan operations allows implicit distribution of test protocol signals such as scan enable (SE) and the scan clocks. The method enables at-speed testing of memory shadow logic.

Aspects of the disclosed technology relate to techniques of test pattern generation based on the cell transition fault model. An assignment for two consecutive clock cycles at inputs of a complex cell in a circuit design is determined based on a gate-level representation of the circuit design. The assignment includes a first transition at one of the inputs which is sensitized by remaining part of the assignment to cause a second transition at an output of the complex cell. A test pattern that generates the assignment at the inputs and propagates a value at the output corresponding to the second clock cycle of the two consecutive clock cycles from the output to an observation point is then derived based on the gate-level representation.

Methods and apparatuses related to the generation of test stimuli are described. In some embodiments, a finite state machine is generated based on a mission profile, and test stimuli are generated based on the mission profile.

This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.

A system and method for testing a device under test (DUT) combines measurement data of field components values made at different sampling locations away from the DUT with computer-aided design layout of the DUT. The combined computer-aided design layout of the DUT and the measurement data can then be displayed for analysis.

This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.

A multiplexer logic device is automatically identified in a hardware definition language of a design. One or more verification properties of the multiplexer logic device are generated to be used in validation of a selected processing condition of the multiplexer logic device. The one or more verification properties and one or more constraints obtained from software and hardware information relating to the multiplexer logic device are provided as input to a formal verification technique. Verification is performed using the formal verification technique to validate the selected processing condition. Based on the performing verification indicating a failure to comply with the selected processing condition, debugging of the multiplexer logic device is performed.

A multiplexer logic device is automatically identified in a hardware definition language of a design. One or more verification properties of the multiplexer logic device are generated to be used in validation of a selected processing condition of the multiplexer logic device. The one or more verification properties and one or more constraints obtained from software and hardware information relating to the multiplexer logic device are provided as input to a formal verification technique. Verification is performed using the formal verification technique to validate the selected processing condition. Based on the performing verification indicating a failure to comply with the selected processing condition, debugging of the multiplexer logic device is performed.

An apparatus for generating Automatic Test Equipment (ATE) testing patterns to test an electronic device-under-test (DUT) that includes electrical circuitry, at least one input port and at least one output port. The apparatus includes a memory and a processor. The memory is configured to store (i) a high-level verification language (HVL) model of the IC, including a model input that models the at least one DUT input port and a model output that models the at least one DUT output port, the HVL model configured to determine, obliviously to the electrical circuitry, a logic state of the model output responsively to a logic state of the model input, and (ii) a simulation program, configured to simulate the HVL model of the DUT. The processor is configured to generate an ATE testing pattern for the DUT by running the simulation program.