A method for repairing logic design includes inserting primary logic gates in a primary logic design path of a logic chip. The method also includes inserting alternative logic gates in an alternate logic design path of the logic chip. The alternate logic design path and the primary logic design path are coupled to multiple fuses. The potentially defective design is repaired by selecting between the alternate logic design path and the primary logic design path with the fuses when the logic design is defective.

A method for repairing logic design includes inserting primary logic gates in a primary logic design path of a logic chip. The method also includes inserting alternative logic gates in an alternate logic design path of the logic chip. The alternate logic design path and the primary logic design path are coupled to multiple fuses. The potentially defective design is repaired by selecting between the alternate logic design path and the primary logic design path with the fuses when the logic design is defective.

An example system includes a processor to receive a template-aware coverage data that tracks probabilities of events in a list of events being hit for a set of test-templates over a first and second predetermined period of time. The processor is to generate a hit prediction score for each combination of unhit event in the events and each test-template in the set of test-templates of the second predetermined period of time. The hit prediction score indicates a probability of an unhit event being hit by a particular test-template in a future third predetermined period of time based on the template-aware coverage data and similarities between the events and the test-templates. The processor is to generate a template score for each test-template based on the hit prediction scores for each test-template. The processor is to select a test-template from the set of test-templates based on the template score.

A device of a data testing environment including a node configured to connect the device to a tester; one or more processors configured to receive from the node an electrical signal alternating between at least a first state and a second state, the first state representing a data transmission trigger and the second state representing a data transmission opportunity; determine a timing of the data transmission opportunity based on the received electrical signal; and send data to the node during the data transmission opportunity in response to receiving the data transmission trigger.

An apparatus is provided that includes a control unit and a memory including computer program code. The apparatus is capable of applying a first signal having a first value and a second signal having a second value to an electronic component and receiving a first feedback signal. The apparatus is capable of determining a first parameter associated with the first feedback signal. The apparatus is capable of applying a third signal having a third value and the second signal to the electronic component and receiving a second feedback signal. The apparatus is capable of determining a second parameter associated with the second feedback signal. The apparatus is capable of applying a fourth signal having a fourth value and the second signal to the electronic component if the first parameter is different from the second parameter.

Disclosed is a semiconductor integrated circuit including a logic circuit, and a plurality of scan flip-flop circuits that hold input data or output data of the logic circuit and are capable of forming a scan chain for executing a scan test of the logic circuit. Each scan flip-flop circuit includes a scan data input part that receives input of scan data for the scan test, a normal data input part that receives input of normal data different from the scan data, and a data holding part capable of separately holding the normal data and the scan data.

Aspects include a system having logic built-in self-test (LBIST) circuitry for use in an integrated circuit with scan chains. The system includes a pattern generator configured for generating scan-in test values for said scan chains; a signature register configured for collecting scan-out responses from said scan chains after a clock sequence; an on-product control generator configured for controlling at least one test parameter; one or more microcode array or memory elements configured to receive inputs to initialize fields in the microcode array or memory elements; and a test controller. The test controller includes a reader component configured for reading test parameters from a field of the microcode array or the memory elements; and a programming component configured for configuring the on-product control generator and the pattern generator with a LBIST pattern according to the read test parameters.

Embodiments include systems and methods for in-system, scan-based device testing using novel narrow-parallel (NarPar) implementations. Embodiments include a virtual automated test environment (VATE) system that can be disposed within the operating environment of an integrated circuit for which scan-based testing is desired (e.g., a chip under test, or CuT). For example, the VATE system is coupled with a service processor and with the CuT via a novel NarPar interface. A sequence controller can drive a narrow set of parallel scan pins on the CuT via the NarPar interface of the VATE system in accordance with an adapted test sequence having bit vector stimulants and expected responses. Responses of the CuT to the bit vector stimulants can be read out and compared to the expected results for scan-based testing of the chip.

A safety circuit for the multi-channel processing of an input signal. The safety circuit includes an analog-to-digital conversion device having a first analog input and a second analog input and at least one digital output for processing the input signal. Furthermore, the safety circuit has a test device which is set up to apply a test signal at the first and/or second input of the A/D conversion device in such a way that the test signal superposes the input signal such that the test signal dominates the input signal.

An embodiment of the present invention provides a computer-implemented method for functional test and diagnostics of integrated circuits. The computer-implemented method includes executing one or more functional test exercisers in a functional execution sequence for a device under test up to one or more checkpoints, applying dynamic clock switching to a clock of the device under test to identify one or more likely causes of a failure identified at the one or more checkpoints, and includes iteratively invoking a portion of the functional execution sequence between a plurality of the checkpoints to progressively isolate the one or more likely causes of the failure as a most likely failure source based at least in part on the applied dynamic clock switching.