Disclosed herein is a pseudo-random binary sequence (PRBS) generator (200) for performing on-chip testing. It comprises of a plurality of lanes (L1-L4), wherein each lane comprises a latch group (Lg1-Lg4) capable of receiving clock signals, wherein a number of latches in each latch group is based on an output sequence to be generated for performing the on-chip testing. Each latch group is having at least one of a flip-flop and a latch is further connected with a plurality of logic gates in such a manner that an output, generated by the at least one of the flip-flop and the latch of each latch group, is provided as an input to the plurality of logic gates.

An integrated circuit (IC) includes logic components and a scan test circuit coupled to the logic components. The IC also includes a scan input pin coupled to the scan test circuit. The IC also includes a scan input/output pin coupled to the scan test circuit. The scan test circuit includes a decoder coupled to at least one of the scan input pin and the scan input/output pin. The decoder includes storage elements configured to store different scan control signals and to output at least one of the different scan control signals in response to a master control signal.

A scan chain may be formed throughout an integrated circuit in which the scan chain is coupled to a set of pins via bi-directional input/output (I/O) buffers. A state machine may be provided to control the scan chain. Decoding logic may monitor states and transitions between states and generate pseudo static control signals in response to certain states and transition sequences in order to free up test pins for use as additional scan data I/O pins using a single JTAG IR. A test pattern may be received from an external tester using the set of I/O pins and buffers operating in parallel. The test pattern may then be provided to combinatorial logic circuitry coupled to the scan chain. A response pattern may be captured in the scan chain. The response pattern may then be provided to the external tester using the same set of I/O pins and buffers operating in parallel.

An integrated circuit (IC) includes logic components and a scan test circuit coupled to the logic components. The IC also includes a scan input pin coupled to the scan test circuit. The IC also includes a scan input/output pin coupled to the scan test circuit. The scan test circuit includes a decoder coupled to at least one of the scan input pin and the scan input/output pin. The decoder includes storage elements configured to store different scan control signals and to output at least one of the different scan control signals in response to a master control signal.

There may be provided a method for validating a monitoring system, the method may include sensing, by at least one sensing element of the monitoring system, a physical parameter; sending sensed information that is related to the physical parameter to a remote computerized system of the monitoring system; applying, by the remote computerized system, a process on the sensed information to provide a response to the sensed information; generating validation information by a generator of the monitoring system; sending the validation information to the remote computerized system; applying, by the remote computerized system, the process on the validation information to provide a response to the validation information; and determining, by a validator of the monitoring system, a validity of the monitoring system based on the response to the validation result.

A scan chain may be formed throughout an integrated circuit in which the scan chain is coupled to a set of pins via bi-directional input/output (I/O) buffers. A state machine may be provided to control the scan chain. Decoding logic may monitor states and transitions between states and generate pseudo static control signals in response to certain states and transition sequences in order to free up test pins for use as additional scan data I/O pins using a single JTAG IR. A test pattern may be received from an external tester using the set of I/O pins and buffers operating in parallel. The test pattern may then be provided to combinatorial logic circuitry coupled to the scan chain. A response pattern may be captured in the scan chain. The response pattern may then be provided to the external tester using the same set of I/O pins and buffers operating in parallel.

An integrated circuit (IC) includes logic components and a scan test circuit coupled to the logic components. The IC also includes a scan input pin coupled to the scan test circuit. The IC also includes a scan input/output pin coupled to the scan test circuit. The scan test circuit includes a decoder coupled to at least one of the scan input pin and the scan input/output pin. The decoder includes storage elements configured to store different scan control signals and to output at least one of the different scan control signals in response to a master control signal.

Fault injection testing for field programmable gate array (FPGA) devices including: interfacing with a FPGA device under test (DUT); imaging a configuration RAM (CRAM) of the FPGA DUT with a first configuration image to define a first operational function of the FPGA DUT where the CRAM includes a plurality of CRAM bits, injecting a plurality of single event upsets into a portion of the plurality of the CRAM bits while the FPGA DUT is operating; concurrently monitoring operations of the FPGA DUT and a reference FPGA device; comparing outputs of the FPGA DUT with outputs of the reference FPGA device during concurrent operations, and if there is a mismatch between the outputs of the FPGA DUT and the reference FPGA, determining that error events have occurred within the FPGA DUT; and storing the error events and CRAM location data associated with corresponding single event upsets in an error log.

Fault injection testing for field programmable gate array (FPGA) devices including: interfacing with a FPGA device under test (DUT); imaging a configuration RAM (CRAM) of the FPGA DUT with a first configuration image to define a first operational function of the FPGA DUT where the CRAM includes a plurality of CRAM bits, injecting a plurality of single event upsets into a portion of the plurality of the CRAM bits while the FPGA DUT is operating; concurrently monitoring operations of the FPGA DUT and a reference FPGA device; comparing outputs of the FPGA DUT with outputs of the reference FPGA device during concurrent operations, and if there is a mismatch between the outputs of the FPGA DUT and the reference FPGA, determining that error events have occurred within the FPGA DUT; and storing the error events and CRAM location data associated with corresponding single event upsets in an error log.

A circuit is described that can include: a first register to store a first value that specifies a first subset of a set of scan chains, wherein the first subset of the set of scan chains includes scan cells that are desired to be masked; a second register to store a second value that specifies, in each shift cycle, a second subset of the set of scan chains, wherein the second subset of the set of scan chains includes scan cells that are desired to be masked; and a masking circuit to mask, in each shift cycle, scan cells in a third subset of the set of scan chains that is an intersection of the first subset of the set of scan chains and the second subset of the set of scan chains.