A sequential circuit includes a data input terminal, a data path, and a redundant feedback loop. The data input terminal receives input data. The data path is connected to the data input terminal and transmits the input data to a data output terminal based on a first clock signal and a second clock signal. The redundant feedback loop is connected to the first data path and stores first data based on at least one of the first or second clock signals when the first data is equal to second data. The first data corresponds to the input data. The second clock signal is a delayed signal of the first clock signal. The second data is delayed data of the first data.

A semiconductor chip, a test system, and a method of testing the semiconductor chip. The semiconductor chip includes a pulse generator configured to generate a test pulse in response to a test request; a logic chain comprising a plurality of logic devices serially connected to each other and transferring the test pulse sequentially; and a detector configured to detect a logic level of an output signal of each of the logic devices and output a detection result indicating a degree of an inter-symbol interference (ISI).

Embodiments of the present disclosure are directed to scan chain systems and methods for inputting repeated sequences of bits to a sequence of flip flops that include multi-bit flip flops and single bit flip flops. One example includes a control circuit that includes a bit counter, a multiplexer, a first group control circuit, and a second group control circuit.

Embodiments of the present disclosure are directed to scan chain systems and methods for inputting repeated sequences of bits to a sequence of flip flops that include multi-bit flip flops and single bit flip flops. One example includes a control circuit that includes a bit counter, a multiplexer, a first group control circuit, and a second group control circuit.

In an aspect, a method of detecting settling of an analog electrical signal in semiconductor device testing includes providing in a semiconductor device tester a device under test (DUT); providing an input signal to the DUT and measuring the input signal; tracking the measurements over time by overlapping the measured input signal with sequential measurement windows that do not overlap with each other, each measurement window spanning a constant measurement period and a constant signal value range while shifting according to measured changes in the input signal such that each measurement window overlaps at least a portion of the measured input signal corresponding to a preceding measurement window; setting a settle count representing a number of consecutive and unshifted measurement windows having unshifted constant signal value ranges; setting a settle count representing a number of consecutive and unshifted measurement windows having unshifted constant signal value ranges; and determining that a settle point has been reached after detecting that the settle count has been met or exceeded by the measured input signal tracked by the sequential measurement windows. Aspects also include an apparatus for adapted performing the aforementioned method and a non-transitory computer storage medium containing instructions that when read by one or more computer processors perform the aforementioned method.