A semiconductor or integrated circuit block including a sense node and a converter circuit, in which the sense node develops a low frequency electrical parameter that is constant or varies at a frequency below a predetermined frequency level, and in which the converter circuit converts the low frequency electrical parameter into an alternating electrical parameter having a frequency at or above the predetermined frequency level sufficient to modulate a laser beam focused within a laser probe area of the converter circuit. The converter may include a ring oscillator, a switch circuit controlled by a clock enable signal, a capacitor having a charge rate based on the low frequency electrical parameter, etc. The laser probe area has a frequency level based on a level of the low frequency electrical parameter to modulate the reflected laser beam for measurement of the electrical parameter by a laser voltage probe test system.

A method of in-system structural testing of a system-on-chip (SoC) using a peripheral interface port is described. The method including enabling a scan interface controller of the SoC through the peripheral interface port. The method also includes streaming structural test patterns in the SoC through the scan interface controller.

An IC includes an IEEE 1149.1 standard test access port (TAP) interface and an additional Off-Chip TAP interface. The Off-Chip TAP interface connects to the TAP of another IC. The Off Chip TAP interface can be selected by a TAP Linking Module on the IC.

This disclosure describes a novel method and apparatus for testing TSVs within a semiconductor device. According to embodiments illustrated and described in the disclosure, a TSV may be tested by stimulating and measuring a response from a first end of a TSV while the second end of the TSV held at ground potential. Multiple TSVs within the semiconductor device may be tested in parallel to reduce the TSV testing time according to the disclosure.

This disclosure describes a novel method and apparatus for testing TSVs within a semiconductor device. According to embodiments illustrated and described in the disclosure, a TSV may be tested by stimulating and measuring a response from a first end of a TSV while the second end of the TSV held at ground potential. Multiple TSVs within the semiconductor device may be tested in parallel to reduce the TSV testing time according to the disclosure.

Systems, methods, and computer program products directed to testing a System-in-a-Package (SIP) using an Automatic Test Equipment (ATE) machine. A functional representation of one or more tests to be performed in the SIP is loaded in a memory located on a load board, the load board located on the ATE machine. A test controller located on at least one of the SIP and the load board is caused to retrieve and store the one or more tests to be performed in the SIP. The test controller is instructed to conduct the one or more tests in the SIP.

A semiconductor device includes at least two die stacked on and electrically coupled to an underlying buffer die, which includes a delay control circuit therein. The delay control circuit is configured to: (i) receive and selectively delay test inputs for testing the at least two die, and (ii) transfer test inputs and a delayed version of the test inputs to a first one of the at least two die and a second one of the at least two die, respectively, during test mode operation. The at least two die may include a vertical stack of N (N>2) die on the buffer die and the delay control circuit may include a timing control circuit therein that is configured to supply test inputs to each of the N die in a staged manner so that commencement of respective test modes within each of the N die using the test inputs are out-of-sync relative to each other.

A ring oscillator for detecting a characteristic degradation of MOSFETs is required to be highly sensitive to NBTI degradation or PBTI degradation. A semiconductor device comprises a ring oscillator and a delay detecting circuit which detects a delay through gate circuits based on the oscillation frequency of the ring oscillator. The ring oscillator comprises an input terminal to which an oscillation control signal is input, an output terminal which outputs an oscillation signal, an oscillation control gate circuit having a first input terminal which is coupled to the input terminal and a second input terminal to which a terminal different from the input terminal is coupled, NAND circuits, and NOR circuits. The NAND and NOR circuits are cascade coupled alternately, plural inputs of the NAND circuits and of the NOR circuits are coupled together, and drive power of the NAND circuits differs from drive power of the NOR circuits.

Test architectures for multi-die chips are provided herein according to embodiments of the present disclosure. In certain aspects, an exemplary test architecture enables an external tester to perform various tests on a multi-die chip that includes multiple dies. In a first test mode, the test architecture enables the external tester to currently perform die-level tests on the multiple dies. In a second test mode, the test architecture enables the external tester to perform a chip-level test on the multi-die chip. The chip-level test may include die-to-die tests for testing interconnections between the multiple dies on the multi-die chip. The chip-level test may also include a boundary input/output (I/O) test for testing external connections between the multi-die chip and one or more devices external to the multi-die chip.

In order to provide a semiconductor device capable of detecting HCI degradation of a semiconductor element in a simple structure, the semiconductor device includes an oscillation circuit including a plurality of logic gates of various driving forces which are formed by transistors and coupled in series, a frequency counter that measures an oscillation frequency of the oscillation circuit, and a comparator that compares the oscillation frequency of the oscillation circuit measured by the frequency counter with a predetermined value.