This disclosure describes a novel .method and apparatus for testing TSVs within a semiconductor device. According to embodiments illustrated and described in the disclosure, a TSV may be tested by stimulating and measuring a response from a first end of a TSV while the second end of the TSV held at ground potential. Multiple TSVs within the semiconductor device may be tested in parallel to reduce the TSV testing time according to the disclosure.

A ring oscillator for detecting a characteristic degradation of MOSFETs is required to be highly sensitive to NBTI degradation or PBTI degradation. A semiconductor device comprises a ring oscillator and a delay detecting circuit which detects a delay through gate circuits based on the oscillation frequency of the ring oscillator. The ring oscillator comprises an input terminal to which an oscillation control signal is input, an output terminal which outputs an oscillation signal, an oscillation control gate circuit having a first input terminal which is coupled to the input terminal and a second input terminal to which a terminal different from the input terminal is coupled, NAND circuits, and NOR circuits. The NAND and NOR circuits are cascade coupled alternately, plural inputs of the NAND circuits and of the NOR circuits are coupled together, and drive power of the NAND circuits differs from drive power of the NOR circuits.

This disclosure describes a novel method and apparatus for testing TSVs within a semiconductor device. According to embodiments illustrated and described in the disclosure, a TSV may be tested by stimulating and measuring a response from a first end of a TSV while the second end of the TSV held at ground potential. Multiple TSVs within the semiconductor device may be tested in parallel to reduce the TSV testing time according to the disclosure.

The present invention relates generally to testing of interconnects in a semiconductor die, and more particularly to testing of semiconductor chips that are three-dimensionally stacked via an interposer. In one aspect, a method for testing an interconnect in a semiconductor die comprises providing the semiconductor die, which includes a plurality of electrical contact elements formed at one or more surfaces of the semiconductor die, at least one interconnect-under-test disposed between a first electrical contact element and a second electrical contact element, and an electrical component electrically coupled between the interconnect-under-test and at least one third electrical contact element.

An IC includes an IEEE 1149.1 standard test access port (TAP) interface and an additional Off-Chip TAP interface. The Off-Chip TAP interface connects to the TAP of another IC. The Off Chip TAP interface can be selected by a TAP Linking Module on the IC.

An IC includes an IEEE 1149.1 standard test access port (TAP) interface and an additional Off-Chip TAP interface. The Off-Chip TAP interface connects to the TAP of another IC. The Off Chip TAP interface can be selected by a TAP Linking Module on the IC.

In order to provide a semiconductor device capable of detecting HCI degradation of a semiconductor element in a simple structure, the semiconductor device includes an oscillation circuit including a plurality of logic gates of various driving forces which are formed by transistors and coupled in series, a frequency counter that measures an oscillation frequency of the oscillation circuit, and a comparator that compares the oscillation frequency of the oscillation circuit measured by the frequency counter with a predetermined value.

An apparatus for a monolithic integrated circuit die is disclosed. In this apparatus, the monolithic integrated circuit die has a plurality of modular die regions. The modular die regions respectively have a plurality of power distribution networks for independently powering each of the modular die regions. Each adjacent pair of the modular die regions is stitched together with a respective plurality of metal lines.

A method and apparatus for testing an electronic component is provided. The method begins when a design-for-test (DFT) mode is entered and at least one sensor is enabled. Sensor results are monitored and determine the number of cores or capture domains that may be tested simultaneously. The sensors include a voltage and temperature sensor, and either or both sensors may be enabled during testing. Maximum and minimum voltage levels for each capture domain determine at what value a voltage drop occurs. The number of cores selected minimizes a voltage drop across the electronic component. Maximum and minimum temperatures across the multiple cores of the electronic component determine the number of clocks that may be operated simultaneously during testing. An apparatus includes an electronic device to be tested, test sensors on the electronic device, and an interface to a test fixture.

An exemplary apparatus for distributing die-specific signals across die stacks includes a die stack and a plurality of signals arranged in a sequence across the die stack. The plurality of signals shift positions in the sequence between a first die and a second die included in the die stack. Various other apparatuses, systems, and methods are also disclosed.