An electronic controller includes: a logic circuit that is reconfigurable based on a reconfiguration instruction; an arithmetic unit that is configured in the logic circuit; a processing controller that transmits the reconfiguration instruction of the arithmetic unit to the logic circuit and that makes the reconfigured arithmetic unit execute predetermined operation; and a testing unit that executes an operation test for an arithmetic unit when the arithmetic unit is reconfigured, and that transmits the result of the operation test to the processing controller as a notice. Here, the processing controller makes the arithmetic unit execute predetermined processing based on the notice received from the testing unit.

Implementations described herein generally relate to detecting excursions in intended geometric features in an integrated circuit substrate. In one implementation, a method includes determining a set of suspect contours in a design window of the integrated circuit substrate based on proximities of a plurality of points of interest in the design window to intended geometric features. The method further includes obtaining a set of imaged contours from one or more images of a defect-free integrated circuit substrate. The method further includes comparing the set of imaged contours to the set of suspect contours to obtain a set of potential excursions from the imaged contours. The method further includes determining a probability that a potential excursion from the set of potential excursions is a valid excursion. The method further includes taking a corrective action based on the determined probability.

A programmable load transient circuit includes a switchable power device for coupling a DUT output to its non-control node in series with a current sense device. A feedback loop is between the current sense device and the power device's control node that includes an integrator including an amplifier coupled to receive a signal that is a function of an average load current (I.sub.Davg) supplied by the DUT from the current sense device and to receive a reference voltage (Vref). The integrator provides an output drive voltage that is coupled to an input of a level shifter which receives a pulse signal or DC level at another of its inputs. The level shifter provides an output waveform or DC voltage to the power device's control node that is a function of I.sub.Davg.

Implementing a circuit design may include detecting, using computer hardware, a net of the circuit design with a hold timing violation, generating, using the computer hardware, a list including each load of the net, and filtering, using the computer hardware, the list based on predetermined criteria by, at least in part, removing each load from the list determined to be non-critical with respect to hold timing. Using the computer hardware, the circuit design is modified by inserting a flip-flop in the net to drive each load remaining on the list, clocking the flip-flop with a clock signal of a start point or an end point of a path traversing the net, and triggering the flip-flop with an opposite clock edge compared to the start point or the end point.

A programmable load transient circuit includes a switchable power device for coupling a DUT output to its non-control node in series with a current sense device. A feedback loop is between the current sense device and the power device's control node that includes an integrator including an amplifier coupled to receive a signal that is a function of an average load current (I.sub.Davg) supplied by the DUT from the current sense device and to receive a reference voltage (Vref). The integrator provides an output drive voltage that is coupled to an input of a level shifter which receives a pulse signal or DC level at another of its inputs. The level shifter provides an output waveform or DC voltage to the power device's control node that is a function of I.sub.Davg.

Programmable shift register with programmable load location (pSRL) for data storage and method thereof is disclosed. A loadable programmable Shift Register (pSR) according to present disclosure receives a programmable input LL that defines where data D is to be loaded from the Load Register when L (Load Control Signal)=1. The loadable Shift Register with programmable load location (pSRL) is configured to obtain L (Load Control Signal), S (Shift Control Signal), LL (Load Location Control Signal), and p (programmable shift value), and wherein the pSRL is adapted to perform loading and shifting of data D based at least on the L, S, LL, and p values.

Implementations described herein generally relate to detecting excursions in intended geometric features in an integrated circuit substrate. In one implementation, a method includes determining a set of suspect contours in a design window of the integrated circuit substrate based on proximities of a plurality of points of interest in the design window to intended geometric features. The method further includes obtaining a set of imaged contours from one or more images of a defect-free integrated circuit substrate. The method further includes comparing the set of imaged contours to the set of suspect contours to obtain a set of potential excursions from the imaged contours. The method further includes determining a probability that a potential excursion from the set of potential excursions is a valid excursion. The method further includes taking a corrective action based on the determined probability.

Methods and apparatus are described for converting a pre-silicon Open Verification Methodology or Universal Verification Methodology (OVM/UVM) device under test (DUT) into a design implementable on a programmable integrated circuit (IC) and for converting the pre-silicon OVM/UVM stimulus from the driver and expected response from the scoreboard into timing aware stimulus-response vectors that can be applied through the tester onto the pads of the programmable IC that contains the implemented design. This approach can handle the clock and other input stimuli changing concurrently in the pre-silicon testbench, and the vectors generated therefrom will be in the proper form so as to work deterministically on the silicon on the tester.

A semiconductor device includes a FIFO, a test data write circuit that sequentially writes a plurality of test data to the FIFO in synchronization with a first clock signal, and a test control circuit that, in parallel with writing of the plurality of test data to the FIFO by the test data write circuit, sequentially reads a plurality of test data stored in the FIFO in synchronization with a second clock signal that is not synchronous with the first clock signal and performs a scan test of a circuit to be tested.

A method includes mapping an AMC into the core fabric of an FPGA and operating the AMC for a select time period. During the select period of time, the AMC counts transition of a signal propagating through the AMC. Timing information based on the counted transitions is stored in a timing model in a memory. The timing information represents an aging characteristic of the core fabric at a time that the AMC is operated. An EDA toolchain uses the timing information in the timing model to generate a timing guard-band for the configurable IC die. The AMC is removed from the core fabric and another circuit device is mapped and fitted into the core fabric using the generated timing guard-band models. The circuit device is operated in the configurable IC die based on the timing guard-band models.