Systems and methods in which circuitry programmability is tested through observing a change in voltage on a circuit node that is affected by the programmability under test. For example, one or more particular circuit node may be identified at which some measurable change in voltage occurs upon a change in state of a programmable circuit under test (PCUT). Thus, by detecting a change in voltage at such a circuit node in association with a programmable state change, embodiments may determine that respective circuit programmability is functional. Test circuitry of embodiments provides for circuitry programmability testing, through observing a change in voltage on a circuit node that is affected by the programmability under test, suitable for testing digital programmability which is deeply embedded in analog circuitry.

A method is described for checking a hardware-configurable logic circuit including circuit areas and including a configuration memory having different subareas for faults, a respective configuration of hardware elements of one of the circuit areas being defined by configuration data stored in an associated subarea of the configuration memory, and when at least one checking requirement in regard to an output signal which is provided by the hardware-configurable logic circuit is met, a fault check of the configuration data being carried out only in those subareas of the configuration memory of the hardware-configurable logic circuit which are involved in generating the output signal.

A scan chain latch circuit, a method of operating a latch circuit in a scan chain, and a computer-readable medium having stored thereon a data structure defining a scan chain latch circuit for instantiation on a semiconductor die are disclosed. In an embodiment, the scan chain latch circuit comprises a first latch for holding one data value, a second latch for holding another data value, and a multiplexor. The one data value is applied to a first data input of the multiplexor and the another data value is applied to a second data input of the multiplexor. An alternating clock signal is applied to a select input of the multiplexor to control the output of the multiplexor, wherein the output of the multiplexor toggles between the two data values held in the two latches at a defined frequency.

Various techniques are provided to implement user specified test registers locally on a PLD for use while the PLD is configured with a user design and tested. In one example, a machine-implemented method includes receiving, from an external test application, a data value at a programmable logic device (PLD) running configured user logic. The method also includes writing the data value into a test register of the PLD. The method also includes providing a control signal from the test register to the configured user logic in response to the data value. The method also includes switching operation of the configured user logic from a first test implementation to a second test implementation in response to the control signal.

An apparatus for a monolithic integrated circuit die is disclosed. In this apparatus, the monolithic integrated circuit die has a plurality of modular die regions. The modular die regions respectively have a plurality of power distribution networks for independently powering each of the modular die regions. Each adjacent pair of the modular die regions is stitched together with a respective plurality of metal lines.

An apparatus has a collection of ring oscillators. An instruction register block is configured to sequentially address and activate each ring oscillator in the collection of ring oscillators. A multiplexer with input lines is connected to each ring oscillator in the collection of ring oscillators and an output line. A pulse counter is connected to the output line of the multiplexer to count the number of oscillations of a selected ring oscillator within a selected time period to form a multiple bit frequency count output signal. A data shift register receives the multiple bit frequency count output signal and produces a serial frequency count output signal.

The present description provides a method of implementation of a test of comparison of a first data word with at least one second data word. An example method includes the following successive steps dividing the first data word into at least one portion; comparing each of the at least one portion of the first data word with at least one corresponding portion of the at least one second data word, by using, for each comparison, a first lookup table; and comparing the results of each of the first lookup tables by using a second lookup table.

An arithmetic operation device executes a test using a partially reconfigurable programmable logic unit, the programmable logic unit includes a test target circuit which is a user circuit, and a non-test circuit which is a user circuit which is not the test target circuit, and the arithmetic operation device includes a configuration control unit which causes the programmable logic unit to form, by partial reconfiguration, a test partition unit which separates the test target circuit and the non-test circuit, and a partition control unit which controls the test partition unit to test the test target circuit.

An apparatus has a collection of ring oscillators. An instruction register block is configured to sequentially address and activate each ring oscillator in the collection of ring oscillators. A multiplexer with input lines is connected to each ring oscillator in the collection of ring oscillators and an output line. A pulse counter is connected to the output line of the multiplexer to count the number of oscillations of a selected ring oscillator within a selected time period to form a multiple bit frequency count output signal. A data shift register receives the multiple bit frequency count output signal and produces a serial frequency count output signal.