An automated test equipment for testing a device under test comprises an on-chip-system-test controller. The on-chip system test controller comprises at least one debug interface or control interface configured to communicate with the device under test. The on-chip-system-test controller optionally comprises at least one high bandwidth interface configured to communicate with the device under test. The on-chip-system-test controller is configured to control a test of a device-under-test which is a system-on-a chip.

Various embodiments may include methods and systems for monitoring characteristics of a system-on-a-chip. Various embodiments may include inputting, from a test data input connection, test data to a first scan chain section including a first group of logic gates located within a first region of the SoC. Various embodiments may include providing, from a first clock gate associated with the first region of the SoC, a clock signal to the first group of logic gates. Various embodiments may include measuring, using a first sensor, the characteristics at a second region of the SoC in response to providing the clock signal to the first group of logic gates. Embodiments may further include processing or analyzing measured characteristics to determine a testing result.

A low power flip-flop includes first to fourth signal generation circuits and an inverter. The first signal generation circuit receives the clock signal, the data input signal, and a first internal signal that is an output of the second signal generation circuit and generates a second internal signal. The inverter receives the first internal signal and generates an inverted first internal signal. The second signal generation circuit receives the first internal signal and the output signal that is an output of the third signal generation circuit, and generates the inverted output signal. The third signal generation circuit receives the clock signal and the inverted output signal and generates the output signal. The fourth signal generation circuit receives the inverted first internal signal, the second internal signal, and the clock signal and generates the first internal signal.

An integrated circuit includes a high-speed interface configured to communicate with a host system for debugging and a debug hub coupled to the high-speed interface. The debug hub is configured to receive a debug command from the host system as memory mapped data. The integrated circuit also includes a plurality of debug cores coupled to the debug hub. Each debug core is coupled to the debug hub by channels. The debug hub is configured to translate the debug command to a data stream and provide the data stream to a target debug core of the plurality of debug cores based on an address specified by the debug command.

A test coverage rate improvement system for pins of tested circuit board and a method thereof are disclosed. In the system, partial pins of a circuit board connector in a tested circuit board are not electrically connected to the boundary scan chip, test pins of the test pin board are pressed with the partial pins by a fixture of a boundary scan interconnect testing workstation to electrically connect the test pins to the partial pins. A test access port controller receives a detection signal for detecting the partial pins, which are not electrically connected to the boundary scan chip, of the circuit board connector through the test pin board from the test adapter card, and determines whether conduction is formed based on the detection signal, thereby achieving the technical effect of improving a test coverage rate for the pins of the tested circuit board.

A circuit is described that can include: a first register to store a first value that specifies a first subset of a set of scan chains, wherein the first subset of the set of scan chains includes scan cells that are desired to be masked; a second register to store a second value that specifies, in each shift cycle, a second subset of the set of scan chains, wherein the second subset of the set of scan chains includes scan cells that are desired to be masked; and a masking circuit to mask, in each shift cycle, scan cells in a third subset of the set of scan chains that is an intersection of the first subset of the set of scan chains and the second subset of the set of scan chains.

A test circuit for testing an integrated circuit includes a plurality of normal flip flops and a modified flip flop, wherein the integrated circuit includes a black box circuit and a plurality of combinational logic circuits. The normal flip flops each includes a first input pin, a second input pin and a first output pin and is configured to temporarily store the input value of the first input pin or the input value of the second input pin according to a scan enable signal. The modified flip flop includes a third input pin, a fourth input pin and a second output pin which are coupled to the black box circuit, the normal flip flops and the combinational logic circuits and is configured to temporarily store the input value of the third input pin or the input value of the fourth input pin according to a scan test mode signal.

Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals.

An implementation of a system disclosed herein includes a decompressor logic with the capability to vary a level of decompression of a scanning input signal based on value of compression program bits and a compressor logic to generate a scanning output signal, the compressor logic including a plurality of XOR logics, wherein the output of the plurality of XOR logics is selected based on the compression program bits.

The present invention provides a reliable method and arrangement for boundary scan testing and debugging newly manufactured multi-chip modules (MCMs) made to identical design specifications with no Known Good Die therein. Advantageously, a first and a second MCM are temporarily linked in tandem for boundary scan testing through a motherboard and daisy-chaining their internal dice, and interlinking the corresponding boundary scan cells of the identical dice of the first and second MCM to (1) run self-test on individual MCMs and mutual test on the MCMs connected in tandem in order to generate an extended Truth Table that includes responses from an array of combined netlists of the first and second MCMs, and (2) to diagnose mismatched bits in the extended Truth Table using a Boundary Scan Diagnostics software so as to identify defects in the first and second MCMs.