Embodiments relate to systems and methods for defect detection and localization in semiconductor chips. In an embodiment, a plurality of registers is arranged in a semiconductor chip. The particular number of registers can vary according to a desired level of localization, and the plurality of registers are geometrically distributed such that defect detection and localization over the entire chip area or a desired chip area, such as a central active region, is achieved in embodiments. In operation, a defect detection and localization routine can be run in parallel with other normal chip functions during a power-up or other phase. In embodiments, the registers can be multi-functional in that they can be used for other operational functions of the chip when not used for defect detection and localization, and vice-versa. Embodiments thereby provide fast, localized defect detection.

Automated test equipment capable of performing a high-speed test of semiconductor devices is presented. The automated test equipment apparatus comprises a computer system comprising a tester processor, wherein the tester processor is communicatively coupled to a plurality of FPGA components. Each of the plurality of FPGA components is coupled to a memory module and comprises: an upstream port operable to receive commands and data from the tester processor; a downstream port operable to communicate with a respective DUT from a plurality of DUTs; and a plurality of hardware accelerator circuits, wherein each of the accelerator circuits is configured to communicate with one of the plurality of DUTs. Each of the plurality of hardware accelerator circuits comprises a pattern generator circuit configurable to automatically generate test pattern data and a comparator circuit configured to compare data.

Automated test equipment (ATE) capable of performing a test of semiconductor devices is presented. The ATE comprises a computer system comprising a system controller communicatively coupled to a tester processor. The system controller is operable to transmit instructions to the processor and the processor is operable to generate commands and data from the instructions for coordinating testing of a plurality of devices under test (DUTs). The ATE further comprises a plurality of FPGA components communicatively coupled to the processor via a bus. Each of the FPGA components comprises at least one hardware accelerator circuit operable to internally generate commands and data transparently from the processor for testing one of the DUTs. Additionally, the tester processor is configured to operate in one of several functional modes, wherein the functional modes are configured to allocate functionality for generating commands and data between the processor and the FPGA components.

A margin testing device includes at least one interface structured to connect to a device under test (DUT) one or more controllers structured to create a set of test signals based on a sequence of pseudo random data and one or more pre-defined parameters, and an output structured to send the set of test signals to the DUT. Methods and a system for testing a DUT with the disclosed margin tester and other testing device are also described.

A device for dynamic signal generation and analysis, which combines an arbitrary waveform generator AWG (3) with a digital signal analysis unit DSAU (23). The two units are interfaced by means of a synchronization unit SU (30), which enables a flexible scheme for controlling how the playback of the waveforms is started as well as synchronizing the recording of the results of the digital signal analysis unit synchronously to specific generated waveforms. The various units of the device are synchronous circuits clocked by a common system clock signal. At least one common numerically controlled oscillator NCO (40) is provided for the arbitrary waveform generator AWG (3) and the digital signal analysis unit DSAU (23).

A test-and-measurement instrument is described. A state machine, corresponding to a regular expression, can be stored in the test-and-measurement instrument. The state machine can be modified to reflect a trigger condition received from a user. The modified state machine can then be used to invoke a trigger when the condition is met in the bits of a bit stream.

The present invention relates to an arrangement for providing a test environment for testing test objects. The arrangement includes a first test case implementation unit and a second test case implementation unit, as well as a first test object and a second test object. In one embodiment, the test environment is configured such that at least the first test case implementation unit is coupled to at least one of the first test object and the second test object for implementing a test case.

A measurement device is described that comprises a measurement unit configured to perform measurements on an electric signal of a device under test while applying at least one measurement parameter for performing the measurements. The measurement device has an integrated direct current source configured to power the device under test. The measurement device also comprises a monitoring unit configured to monitor at least one monitoring parameter of the direct current source. The measurement device has a control unit configured to control the measurement parameter. Further, a method for measuring a device under test is described.

An automated test equipment (ATE) apparatus is presented. The apparatus comprises a computer system comprising a system controller, wherein the system controller is communicatively coupled to a site module board comprising a tester processor and an FPGA wherein the system controller is operable to transmit instructions to the tester processor, and wherein the tester processor is operable to generate commands and data from the instructions for coordinating testing of a device under test (DUT) wherein the site module board comprises a compact form factor suitable for use during prototyping, and wherein the site module board is operable to be coupled with a DUT. Further, the FPGA is communicatively coupled to the tester processor, wherein the FPGA comprises at least one hardware accelerator circuit operable to internally generate commands and data transparently from the tester processor for testing the DUT.

A testing system uses different operating systems to test electronic products. The testing system includes a master computer, a slave computer and a relay. A first operating system is installed in the master computer. A second operating system is installed in the slave computer. The master computer and the slave computer are connected with each other through RS-232 ports. The relay is connected with the master computer, the slave computer and an under-test product. By changing the voltage level state of specified pins of the RS-232 ports, the master computer notifies the slave computer to test the under-test product. Moreover, by controlling the relay, the connection between the master computer and the under-test product is switched to the connection between the slave computer and the under-test product. Consequently, the under-test product is tested by the slave computer.