An optical integrated circuit device includes a semiconductor substrate and a first waveguide made of a first material and disposed over the semiconductor substrate. The first waveguide includes a parallel region and a tapered region. The optical integrated circuit device further includes a first cladding structure disposed over and surrounding the parallel region of the first waveguide, a first extension made of the first material and disposed over the semiconductor substrate, and an electrostatic discharge (ESD) protection structure electrically coupled to the first extension. The first extension physically contacts the parallel region of the first waveguide. The first extension includes a first portion within the first cladding structure and a second portion outside the first cladding structure.

An integrated circuit device is described. The integrated circuit device comprises a substrate having transmitter for receiving a signal to be transmitted to a receiver of the substrate by way of a transmission channel; a first plurality of contacts adapted to receive a first integrated circuit die, wherein a contact of the first plurality of contacts is adapted to receive the signal to be transmitted by the transmitter; a second plurality of contacts adapted to receive a second integrated circuit die, wherein a contact of the second plurality of contacts is adapted to receive the signal transmitted by the transmitter and received by the receiver; a first resistive element coupled between a contact of the first plurality of contacts and the transmitter; and a second resistive element coupled between a contact of the second plurality of contacts and the receiver. A method of transmitting data in an integrated circuit is also described.

Provided are: a display panel whereby a frame can be narrowed, while ensuring conduction between substrates; a display device; and a method for manufacturing the display panel. The display panel is provided with: a first substrate having a surface, on which an electrode layer is formed; a second substrate having a surface, on which a wiring path for supplying the electrode layer with signals is formed; and a sealing section that defines a space sealed between the first substrate surface and the second substrate surface, which are facing each other. The display panel is also provided with a columnar section that electrically connects the electrode layer to the wiring path. The columnar section is formed at a position in contact with the sealing section.

This disclosure relates to optical module. In one implementation, the optical module includes a multi-layer circuit board, a first optical chip, a second optical chip, and a processor, wherein a surface layer on a same side of the circuit board comprises a first row of edge connector pins and a second row of edge connector pins; the first row of edge connector pins comprise a first power pin; the second row of edge connector pins comprise a second power pin; the first power pin is connected to the first optical chip; the second power pin connected to the second optical chip and the processor; the first power pin and the second power pin are aligned along a same direction and are arranged at a same position among the first row of edge connector pins and the second row of edge connector pins; and the first power pin is electrically connected to the second power pin. In another implementation, the first power pin and the second power pin is not electrically connected and wherein the circuit board further comprises a power delay circuit between the second power pin and the processor.

An integrated photo detector with enhanced electrostatic discharge damage (ESD) protection. The integrated photo detector includes a first photodiode formed in the SOI substrate and associated with a first p-electrode and a first n-electrode. Additionally, the integrated photo detector includes a second photodiode formed in the SOI substrate associated with a second p-electrode and a second n-electrode forming a capacitance no larger than a few femto Faradays. Moreover, the integrated photo detector includes a first electrode and a second electrode disposed respectively on the SOI substrate. The first/second electrode is respectively connected to the first p/n-electrode via a first/second metallic layer patterned with a reduced width from the first/second electrode to the first p/n-electrode and connected to the second p/n-electrode via a first/second metallic wire to make a parallel coupling between the first photodiode and the second photodiode with an ESD threshold of about 100V.

An optical integrated circuit device includes an electrically insulating substrate, an optical connection disposed at a boundary of the optical integrated circuit, and a first electrostatic discharge (ESD) protection structure in direct contact with and electrically coupled to the first waveguide. The optical connection includes a first waveguide. The first waveguide is disposed on the electrically insulating substrate and configured to transmit an optical signal. The first ESD protection structure is both electrically non-insulating and substantially optically transparent to the optical signal. An ESD diode including an anode and a cathode is electrically coupled to the first ESD protection structure. A ground connection is electrically coupled to the anode of the ESD diode.

Various embodiments of a photonic integrated circuit (PIC) are described herein. A PIC, functioning as a coherent receiver, may include optical components such as an optical coupler, a directional coupler, a beam splitter, a polarizing beam rotator-splitter, a variable optical attenuator, a monitor photodiode, 90-degree hybrid mixer, and a waveguide photodiode. The PIC may also include electrical components such as an electrode, a capacitor, a resistor and a Zener diode.

This disclosure relates to optical module. In one implementation, the optical module includes a multi-layer circuit board, a first optical chip, a second optical chip, and a processor, wherein a surface layer on a same side of the circuit board comprises a first row of edge connector pins and a second row of edge connector pins; the first row of edge connector pins comprise a first power pin; the second row of edge connector pins comprise a second power pin; the first power pin is connected to the first optical chip; the second power pin connected to the second optical chip and the processor; the first power pin and the second power pin are aligned along a same direction and are arranged at a same position among the first row of edge connector pins and the second row of edge connector pins; and the first power pin is electrically connected to the second power pin. In another implementation, the first power pin and the second power pin is not electrically connected and wherein the circuit board further comprises a power delay circuit between the second power pin and the processor.

An integrated photo detector with enhanced electrostatic discharge damage (ESD) protection. The integrated photo detector includes a first photodiode formed in the SOI substrate and associated with a first p-electrode and a first n-electrode. Additionally, the integrated photo detector includes a second photodiode formed in the SOI substrate associated with a second p-electrode and a second n-electrode forming a capacitance no larger than a few femto Faradays. Moreover, the integrated photo detector includes a first electrode and a second electrode disposed respectively on the SOI substrate. The first/second electrode is respectively connected to the first p/n-electrode via a first/second metallic layer patterned with a reduced width from the first/second electrode to the first p/n-electrode and connected to the second p/n-electrode via a first/second metallic wire to make a parallel coupling between the first photodiode and the second photodiode with an ESD threshold of about 100V.

An integrated photo detector with enhanced electrostatic discharge damage (ESD) protection. The integrated photo detector includes a first photodiode formed in the SOI substrate and associated with a first p-electrode and a first n-electrode. Additionally, the integrated photo detector includes a second photodiode formed in the SOI substrate associated with a second p-electrode and a second n-electrode forming a capacitance no larger than a few femto Faradays. Moreover, the integrated photo detector includes a first electrode and a second electrode disposed respectively on the SOI substrate. The first/second electrode is respectively connected to the first p/n-electrode via a first/second metallic layer patterned with a reduced width from the first/second electrode to the first p/n-electrode and connected to the second p/n-electrode via a first/second metallic wire to make a parallel coupling between the first photodiode and the second photodiode with an ESD threshold of about 100V.