An array substrate, includes: a substrate, a first metal layer, a first buffer layer, and an active layer, a gate insulating layer, a second metal layer, a first insulating layer, a third metal layer and a first planarization layer. The first metal layer is electrically connected with the first doped area of the active layer through the bridge layer of the second metal layer. The third metal layer is electrically connected with the second doped area of the active layer. The array substrate of the present disclosure reduces a size of a thin film transistor by stacking the first metal layer, the second metal layer, and the third metal layer, thereby increasing pixel density. A display panel is also provided.

A liquid crystal display panel includes a first and second base substrates, a liquid crystal layer and an optical compensation layer. In the liquid crystal layer, a first alignment film is configured to make a part of second liquid crystal molecules proximate to the first alignment film have a first pretilt angle, a second alignment film is configured to make a part of second liquid crystal molecules proximate to the second alignment film have a second pretilt angle. In the optical compensation layer, a third alignment film is configured to make first liquid crystal molecules proximate to the third alignment film have a third pretilt angle. A direction of orthogonal projections of long axes of the first liquid crystal molecules is parallel to or perpendicular to a direction of orthogonal projections of long axes of second liquid crystal molecules anchored by the first alignment film and the second alignment film.

A liquid crystal display device according to FFS technology is provided, which sufficiently provides a common electrode with common electric potential and improves an aperture ratio of pixels. A pixel electrode is formed of a first layer transparent electrode. A common electrode made of a second layer transparent electrode is formed above the pixel electrode interposing an insulation film between them. The common electrode in an upper layer is provided with a plurality of slits. The common electrode extends over all the pixels in a display region. An end of the common electrode is disposed on a periphery of the display region and connected with a peripheral common electric potential line that provides a common electric potential Vcom. There is provided neither an auxiliary common electrode line nor a pad electrode, both of which are provided in a liquid crystal display device according to a conventional art.

The present application provides a liquid crystal display (LCD) panel and an LCD device. In the LCD panel, a first metal layer and a second metal layer are connected to a metal connection layer through a first via hole and a second via hole, respectively. A difference between a depth of the first via hole and a depth of the second via hole is smaller than a sum of thicknesses of a gate insulating layer, an active layer, and the second metal layer. Accordingly, the depth of the first via hole is reduced, a length of the meal connection layer in the first via hole is shortened, and an impedance is lowered.

A display panel and a display device are disclosed. The display panel includes a first substrate, a second substrate, and a spacer. The first substrate includes a substrate, a signal line, a planarization layer, and an electrode layer. The electrode layer is arranged on the planarization layer and is located in the pixel regions. The electrode layer includes at least a trunk and a plurality of branches. The plurality of branches are disposed at intervals and connected to the trunk. A groove is defined in the planarization layer in a region adjacent to the spacer. The groove corresponds to the electrode layer, so that the portion of the electrode layer in the region adjacent to the spacer is embedded in the groove.

An array substrate, a display panel and a method of fabricating the array substrate are disclosed. The array substrate is applied to the display panel, and includes a substrate, multiple scan lines, multiple data lines, a color filter layer, and a planarization layer. The color filter layer at least includes a plurality of first color filters, at least one of which has a raised portion in a region adjacent to the respective data line, and a middle portion in a region away from the respective data line, where a thickness of the raised portion is greater than that of the middle portion. The planarization layer defines at least one first elongated groove corresponding to the raised portion and extending along an extending direction of the data lines. The pixel electrode branch and/or the common electrode branch disposed corresponding to the raised portion is disposed in the respective first elongated groove.

According to an aspect of the present disclosure, a liquid crystal display device includes a lower substrate including a black matrix and a color filter; an upper substrate disposed to be opposite to the lower substrate; a thin film transistor which on the upper substrate to be opposite to the color filter, and including a gate electrode, an active layer, a source electrode, and a drain electrode; at least one insulting layer disposed on the thin film transistor; a pixel electrode disposed on the insulating layer and electrically connected to the drain electrode; and a common electrode spaced apart from the pixel electrode, and the gate electrode includes a first gate conductive layer including a transparent conductive material, a second gate conductive layer including a first transition metal oxide and a second transition metal oxide, and a third gate conductive layer formed of an opaque conductive layer.

A liquid crystal display device according to FFS technology is provided, which sufficiently provides a common electrode with common electric potential and improves an aperture ratio of pixels. A pixel electrode is formed of a first layer transparent electrode. A common electrode made of a second layer transparent electrode is formed above the pixel electrode interposing an insulation film between them. The common electrode in an upper layer is provided with a plurality of slits. The common electrode extends over all the pixels in a display region. An end of the common electrode is disposed on a periphery of the display region and connected with a peripheral common electric potential line that provides a common electric potential Vcom. There is provided neither an auxiliary common electrode line nor a pad electrode, both of which are provided in a liquid crystal display device according to a conventional art.

A liquid crystal display panel (100) comprises a first polarizer (110) and a second polarizer (170), a first liquid crystal layer (130) disposed between the first polarizer (110) and the second polarizer (170), and an optical compensation layer (140) disposed between the first liquid crystal layer (130) and one of the first polarizer (110) and the second polarizer (170). A transmission axis of the first polarizer (110) is perpendicular to a transmission axis of the second polarizer (170). The first liquid crystal layer (130) includes first liquid crystal molecules (130′). An included angle (γ) between an orthographic projection of an optical axis of a first liquid crystal molecule (130′) on the first polarizer (110), which is perpendicular to an orthographic projection of an optical axis of the optical compensation layer (140) on the first polarizer (110), and the transmission axis of the first polarizer (110) is an acute angle,

An electronic device is provided, which includes a first substrate, a second substrate, a data line, a first spacer, and a second spacer. The first spacer and the data line are on the first substrate, and the second spacer is on the second substrate and between the first spacer and the second substrate. Part of the first spacer does not overlap with the second spacer, and the first spacer includes a first portion, a second portion, and a third portion. The first portion overlaps with the second spacer. The first portion connects between the second portion and the third portion. The data line has a first part and a second part. The first part overlaps with the first portion. The second part does not overlap with the first portion. A maximum width of the first part is less than a maximum width of the second part.