A halftone mask, a manufacturing method of a display panel, and an ultraviolet mask are disclosed. The halftone mask includes a substrate, a plurality of light-blocking parts, and a plurality of semi-transmissive parts. Wherein, the semi-transmissive parts correspond to a thinned patterning area of a first target object and a hollowed patterning area of a second target object.

A display device includes a first transistor having an oxide semiconductor layer, a gate wiring opposite the oxide semiconductor layer, a gate insulating layer between the semiconductor layer and the gate wiring, a first insulating layer including at least one insulating layer having a first contact hole outside the gate wiring, a planarization film having a second contact hole overlapping the first contact hole, a first transparent conductive layer including an area overlapping the gate wiring, a second insulating layer covering a side of the second contact hole, a second transparent conductive layer in contact with the oxide semiconductor layer through the first and second contact hole, a first resin filling the first and second contact hole coated by the second transparent conductive layer, and a third transparent conductive layer on the second transparent conductive layer and the first resin.

A light shielding element substrate includes a substrate, a transparent island structure and a first light shielding layer. The transparent island structure is located on the substrate. The first light shielding layer is located on the transparent island structure. The first light shielding layer is overlapping with a part of the top surface of the transparent island structure. The first light shielding layer has a first through hole overlapping the top surface of the transparent island structure.

A display panel is provided. The display panel includes a bank layer and a quantum dots material layer on a base substrate. The bank layer defines a plurality of bank apertures. The quantum dots material layer includes a plurality of quantum dots blocks respectively in at least some of the plurality of bank apertures. At least a portion of the bank layer between two adjacent bank apertures includes a first surface, a second surface opposite to the first surface, a third surface connecting the first surface and the second surface closer to a first bank aperture, and a fourth surface connecting the first surface and the second surface closer to a second bank aperture. At least a portion of a third surface or a fourth surface of a portion of the bank layer between two adjacent bank apertures is a wavy surface including alternating convex and concave portions.

An array substrate and a manufacturing method thereof and a display device are provided. The array substrate includes a base substrate, a polarizer, a plurality of active elements, a first organic protective layer and a first inorganic protective layer. The polarizer is located on a first side of the base substrate; the plurality of active elements are arranged in an array form and provided on a second side of the base substrate opposite to the first side; the first organic protective layer is located on a side of the polarizer facing away from the base substrate and covers the polarizer; and the first inorganic protective layer is located on a side of the first organic protective layer facing away from the polarizer and covers the first organic protective layer.

An array substrate includes: a first substrate (10), including a plurality of sub-pixel regions (101) arranged in an array along a row direction (X) and a column direction (Y); a pixel circuit layer, including a plurality of sub-pixel circuits; a planarization layer (17), provided with a first via hole (170) located in the sub-pixel regions (101), and includes at least one pattern portion (171), the pattern portion (171) includes a plurality of pattern units (171a) arranged in an array along the row direction (X) and the column direction (Y); and a reflective electrode layer, wherein the reflective electrode layer includes a plurality of reflective electrodes (18) that are mutually disconnected, each of the reflective electrodes (18) is located in one of the sub-pixel regions (101) and is electrically connected to the sub-pixel circuit through the first via hole (170).

A display device including: a first substrate; first through third subpixel electrodes which are disposed on the first substrate to neighbor each other; a second substrate opposing the first substrate; a first wavelength conversion pattern at least partially overlapping the first subpixel electrode and a second wavelength conversion pattern at least partially overlapping the second subpixel electrode; a first light transmission pattern at least partially overlapping the third subpixel electrode and a second light transmission pattern disposed between the first wavelength conversion pattern and the second wavelength conversion pattern; and a low refractive layer which has a lower refractive index than the first and second wavelength conversion patterns.

The embodiments of the present disclosure provide a display panel. The display panel includes a first substrate, a second substrate disposed opposite to the first substrate, and a liquid crystal layer between the first substrate and the second substrate, a plurality of first electrodes disposed on a side, close to the second substrate, of the first substrate and spaced apart at intervals, a first dielectric layer for planarizing the plurality of first electrodes, a second dielectric layer disposed on a side, close to the liquid crystal layer, of the first dielectric layer, a light shielding portion disposed on the side, close to the liquid crystal layer, of the second substrate, and a control circuit configured to apply a voltage between the first electrode and the second electrode so that the liquid crystal layer is in a first state or a second state.

According to one embodiment, a display device includes a first substrate, a second substrate opposing the first substrate, a liquid crystal layer disposed between the first substrate and the second substrate and a sealant which seals the liquid crystal layer. The first substrate includes a pixel electrode disposed in a display area, a peripheral circuit disposed in a peripheral area surrounding the display area and a shield electrode disposed in a position overlapping the peripheral circuit in plan view. The second substrate includes a common electrode disposed in the display area and opposing the pixel electrode. The shield electrode and the common electrode do not overlap each other in plan view.

To prevent a phenomenon that an alignment film material is difficult to flow into the through-hole where a diameter of a through-hole for connecting between a pixel electrode and a source electrode is reduced. A liquid crystal display device comprising a TFT substrate having pixels each including a common electrode formed on an organic passivation film, an interlayer insulating film formed so as to cover the common electrode, a pixel electrode having a slit and formed on the interlayer insulating film, a through-hole formed in the organic passivation film and the interlayer insulating film, and a source electrode electrically conducted to the pixel electrode via the through-hole. A taper angle at a depth of D/2 of the through-hole is equal to or more than 50 degrees. The pixel electrode covers part of a side wall of the through-hole but does not cover the remaining part of the side wall of the through-hole. This configuration facilitates the alignment film material to flow into the through-hole, thereby solving a thickness unevenness of the alignment film in vicinity of the through-hole.