A pixel structure, an array substrate and a display device is provided. The pixel structure includes a base substrate, and a gate layer and a source/drain layer arranged on the base substrate. An overlapping region is present between the gate layer and the source/drain layer, and the gate layer and/or the source/drain layer comprises a hollow structure located in the overlapping region.

A pixel array includes multiple first signal lines, multiple second signal lines, multiple third signal lines and multiple pixel structures. The first signal lines are arranged in parallel. The second signal lines are arranged in parallel and intersecting with the first signal lines to demarcate a plurality of first unit regions and a plurality of second unit regions. Each of the second signal lines electrically connects to one of the first signal lines, the second signal lines are arranged in different pitches, and an area of each of the second unit regions is smaller than an area of each of the first unit regions, and the first unit regions and the second unit regions are alternately arranged. An orthographic projection of each of the pixel electrodes on the substrate is non-overlapped with or incompletely overlapped with an orthographic projection of the corresponding second signal lines on the substrate.

A channel layer is formed of an oxide semiconductor. A first insulating film is provided on the channel layer, a source line, and a drain electrode, and includes a drain contact hole which reaches the drain electrode. A pixel electrode is provided on the first insulating film, includes a connection conductive layer which is connected to the drain electrode by the drain contact hole, and is formed of a transparent conductive material. The pixel electrode is covered with a second insulating film. A common electrode is provided on the second insulating film, includes an opening which faces the pixel electrode in a thickness direction, and is formed of a transparent conductive material. A metal layer, in conjunction with a part of the common electrode, forms a laminated structure, and includes a light-shield part which overlaps the channel layer at least partially in plan view.

An active matrix substrate includes a substrate, a pixel TFT that is supported by the substrate, provided corresponding to each of a plurality of pixel areas, and includes an oxide semiconductor layer, an organic insulating layer disposed above at least the oxide semiconductor layer of the pixel TFT, and an inorganic insulating layer disposed in contact with an upper surface of the organic insulating layer on the organic insulating layer. The organic insulating layer and the inorganic insulating layer are provided with a plurality of dual-layer hole structure portions, each of the dual-layer hole structure portions includes a through-hole provided in the inorganic insulating layer and a bottomed hole provided in the organic insulating layer and positioned below the through-hole, and the through-hole is positioned on an inner side of an outer edge of the bottomed hole when viewed from a normal direction of the substrate.

A display device with favorable display quality is provided. A display portion where a plurality of pixels is arranged in a matrix is divided into Region A and Region B, i.e., regions on the upstream side and the downstream side of a scanning direction. A signal line for supplying an image signal is provided in each of Region A and Region B. Region A and Region B adjoin each other such that a boundary line showing the boundary between the regions is bent. Bending the boundary line suppresses formation of a stripe in a boundary portion. For example, in a given column, the total number of pixels electrically connected to a signal line in Region A is made different from the total number of pixels electrically connected to a signal line in Region B.

An array substrate and a display device is disclosed. The array substrate includes a base substrate, a plurality of gate lines and a plurality of data lines arranged to intersect each other on the base substrate, a pixel electrode arranged in a region defined by an adjacent gate line and an adjacent data line, and a thin film transistor arranged at an intersection of the gate lines and the data lines. A drain of the thin film transistor is connected with the pixel electrode through a via hole. The gate lines further include a widening portion between adjacent data lines. The widening portion comprises a recess structure. An orthogonal projection of the recess structure on the base substrate at least partly overlaps that of the drain of the thin film transistor on the base substrate.

Display backplanes and pixel element structures are described. In an embodiment, a pixel electrode is located between two stacked data lines, with a left edge of the pixel electrode being separated from a first lower data line by approximately a same distance as a right edge of the pixel electrode is separated from a second lower data line.

According to one embodiment, a liquid crystal display device includes a first interlayer insulation film located above a first gate line and a second gate line, a first common electrode extending over the first interlayer insulation film, a second interlayer insulation film covering the first common electrode, and a first pixel electrode disposed on the second interlayer insulation film. The first common electrode extends, from a position opposed to the first pixel electrode, beyond the source line in the first direction and beyond the gate line in the second direction.

According to one embodiment, a liquid crystal display device includes a first substrate including a semiconductor layer including a first extension portion and a second extension portion, a gate line, a first common electrode opposed to at least the second extension portion, a source line extending above the second extension portion, a pixel electrode including a main pixel electrode, a second common electrode including a second main common electrode opposed to the source line, and a first alignment film.

The present disclosure provides a display substrate, including: a wiring mounting region. The wiring mounting region includes first wires and second wires, each of the first wires intersecting with one or more of the second wires, thereby defining one or more intersectional regions; and a semiconductor pattern between the first wire and the one or more second wires, the semiconductor pattern having at least one cross-sectional width covering at least a portion of at least one of the intersectional regions.