The present disclosure discloses a panel structure of flat displays and the manufacturing method thereof. The panel structure includes a first signal line, a second signal line, a transparent conductive film, and a scanning line. The transparent conductive film includes a first branch, a second branch, and a third branch. A first end of the first branch and a first end of the second branch are connected by a predetermined first angle, and a second end of the second branch and a first end of the third branch are connected by a predetermined second angle. The first branch, the second branch, and the third branch form the arch-shaped frame. The first signal line connects to the second end of the first branch, and the second signal line connects to the second end of the third branch. The scanning line passes through the arch-shaped frame along a first direction.

A display device includes a first transistor provided with an oxide semiconductor layer, a first gate wiring facing the oxide semiconductor layer and a first gate insulating layer between the oxide semiconductor layer and the first gate wiring, a first transparent conductive layer provided on at least a first insulating layer on the first transistor, the first transparent conductive layer having an area overlapping the gate wiring and being in contact with the oxide semiconductor layer in a first contact area not overlapping the gate wiring, a second transparent conductive layer provided above at least a second insulating layer on the first transparent conductive layer and being in contact with the first transparent conductive layer at a second contact area overlapping the gate wiring, and a third transparent conductive layer provided between the second transparent conductive layer and the second insulating layer.

A pixel unit, including: a pixel electrode, a gate electrode, a gate electrode line connected with the gate electrode, a source electrode, a data line connected with the source electrode, a second electrode disposed in a same layer as the pixel electrode, a first drain electrode connected with the pixel electrode, and a second drain electrode connected with the second electrode; the first drain electrode and the second drain electrode and the source electrode are provided with a channel therebetween, and the first drain electrode and the second drain electrode do not contact each other; along a direction of the data line, the edge of the second electrode is parallel with the edge of the pixel electrode and the two do not contact. An array substrate, a pixel driving method and a display device are further disclosed for overcoming the phenomenon of light leakage of the edge of the pixel unit caused by reduction of the width of the black matrix.

A display device includes an array substrate having a first data line along a first direction. The array substrate further includes a first insulating layer and a common electrode. The insulating layer disposes on the first data line. The common electrode disposes on the insulating layer and includes a plurality of sub-common electrode rows disposed along the second direction which is different from the first direction. The sub-common electrode rows extend along the second direction. The sub-common electrode rows include a first portion, a second portion separated from the first portion, and a connection portion connecting the first and second portions. The first data line overlapping the sub-common electrode rows, and the number of first portions overlapping the first data line is greater than the number of connection portions overlapping the first data.

The present invention provides a thin film transistor array substrate and a liquid crystal display panel. The thin film transistor array substrate comprises: a substrate, and the substrate comprises a first surface and a second surface oppositely located; a thin film transistor array, located on the first surface; a common electrode layer, and the common electrode layer is isolated from the thin film transistor array, and the common electrode layer comprises a plurality of first strip holes; a sensing electrode layer, and the sensing electrode layer is isolated from the common electrode layer, and the sensing electrode layer comprises a plurality of sensing units and a plurality of sensing wires, and the sensing units are distributed in row and column, and the sensing wires are electrically coupled to the sensing units of each row or each column respectively, and the sensing wires are located corresponding to the first strip holes.

An object is to provide a semiconductor device having a structure in which parasitic capacitance between wirings can be efficiently reduced. In a bottom gate thin film transistor using an oxide semiconductor layer, an oxide insulating layer used as a channel protection layer is formed above and in contact with part of the oxide semiconductor layer overlapping with a gate electrode layer, and at the same time an oxide insulating layer covering a peripheral portion (including a side surface) of the stacked oxide semiconductor layer is formed. Further, a source electrode layer and a drain electrode layer are formed in a manner such that they do not overlap with the channel protection layer. Thus, a structure in which an insulating layer over the source electrode layer and the drain electrode layer is in contact with the oxide semiconductor layer is provided.

The array substrate of embodiments of the present invention uses the adjustment dielectric layer to reduce parasitic capacitance between the gate metal layer and the electrode layer, thus avoiding the dark streak phenomenon due to the fringing electric field and the surrounding environment and improving display quality.

A display device, comprising: a first pixel row including a first pixel electrode and a second pixel electrode that are arranged in a first direction; a second pixel row; a third pixel row; a first source line and a second source line that extend in a second direction between the first pixel electrode and the second pixel electrode; a first gate line that extends in the first direction between the first pixel row and the second pixel row; a second gate line that extends in the first direction between the second pixel row and the third pixel row; a first end connection wiring that connects the first gate line to the second gate line at an end portion of the second pixel row; and one or more first cross connection wirings that transverse the second pixel row and connect the first gate line to the second gate line.

The invention provides a thin film transistor (TFT) array substrate, a manufacturing method thereof, and a display panel. The TFT array substrate includes a substrate. A buffer layer and a TFT functional layer are sequentially disposed on the substrate. The TFT functional layer includes an active layer (Active), a gate insulating layer (GI), a gate layer (GE), an interlayer insulating layer (ILD), and a source-drain layer (SD) that are sequentially disposed on the buffer layer. An inorganic insulating layer is disposed on the source-drain layer, and a backside indium tin oxide (BITO) layer, a passivation layer (PV), and a top indium tin oxide (TITO) layer are sequentially disposed on the inorganic insulating layer. The invention provides the TFT array substrate. The TFT array substrate adopts a new functional layer structure design, which can effectively reduce production cost and cycle time of the TFT array substrate.

Disclosed in the disclosure are a display panel and a display device. The display panel includes: a first base substrate; a plurality of scan signal lines arranged on a side of the first base substrate; a plurality of data signal lines arranged on sides, facing away from the first base substrate, of the scan signal lines; and first shielding parts arranged on sides, facing away from the scan signal lines, of the data signal lines, wherein each first shielding part is of a strip structure, and in each sub-pixel unit, both sides of the data signal line are each provided with one first shielding part.