According to an aspect, a substrate includes an insulating base material, a pixel electrode provided on one surface side of the base material, a common electrode provided between the base material and the pixel electrode. All sides on an outer periphery of the common electrode are located inside the pixel electrode in a plan view.

A first substrate includes: a first base material including an insulating layer; and a partition wall disposed on the insulating layer. The insulating layer and the partition wall are formed of a resin material. The partition wall has a higher hardness than the insulating layer. A protective film that protects the insulating layer is disposed on a surface of the insulating layer. A portion of the protective film is located between the partition wall and the insulating layer.

A first substrate includes: a first base material including an insulating layer; and a partition wall disposed on the insulating layer. The insulating layer and the partition wall are formed of a resin material. The partition wall has a higher hardness than the insulating layer. A protective film that protects the insulating layer is disposed on a surface of the insulating layer. A portion of the protective film is located between the partition wall and the insulating layer.

According to one embodiment, a semiconductor substrate includes a first basement, a gate line, a source line, an insulating film, a first pixel electrode, and a first transistor and a second transistor connected parallel at positions between the source line and the first pixel electrode. Each of a first semiconductor layer of the first transistor and a second semiconductor layer of the second transistor includes a first region, a second region, and a channel region. The first semiconductor layer and the second semiconductor layer are in contact with a first surface that is a surface of the insulating film on the source line side. The channel region of each of the first semiconductor layer and the second semiconductor layer wholly overlaps the gate line.

According to one embodiment, a semiconductor substrate includes a first basement, a gate line, a source line, an insulating film, a first pixel electrode, and a first transistor and a second transistor connected parallel at positions between the source line and the first pixel electrode. Each of a first semiconductor layer of the first transistor and a second semiconductor layer of the second transistor includes a first region, a second region, and a channel region. The first semiconductor layer and the second semiconductor layer are in contact with a first surface that is a surface of the insulating film on the source line side. The channel region of each of the first semiconductor layer and the second semiconductor layer wholly overlaps the gate line.

Provided is an electronic paper. The electronic paper includes: an array substrate and a cover plate that are arranged oppositely, and an electrophoretic layer disposed between the array substrate and the cover plate. The array substrate includes: a substrate, a pixel electrode disposed on the substrate, a first auxiliary electrode disposed on the substrate and electrically connected to the pixel electrode, and a second auxiliary electrode disposed between the pixel electrode and the first auxiliary electrode, wherein the second auxiliary electrode is insulated from the pixel electrode and the first auxiliary electrode. An orthographic projection of the second auxiliary electrode on the substrate is at least partly overlapped with an orthographic projection of the pixel electrode on the substrate, and is at least partly overlapped with an orthographic projection of the first auxiliary electrode on the substrate.

Provided is an electronic paper. The electronic paper includes: an array substrate and a cover plate that are arranged oppositely, and an electrophoretic layer disposed between the array substrate and the cover plate. The array substrate includes: a substrate, a pixel electrode disposed on the substrate, a first auxiliary electrode disposed on the substrate and electrically connected to the pixel electrode, and a second auxiliary electrode disposed between the pixel electrode and the first auxiliary electrode, wherein the second auxiliary electrode is insulated from the pixel electrode and the first auxiliary electrode. An orthographic projection of the second auxiliary electrode on the substrate is at least partly overlapped with an orthographic projection of the pixel electrode on the substrate, and is at least partly overlapped with an orthographic projection of the first auxiliary electrode on the substrate.

A total internal reflection display includes a sub-pixel, a reflecting layer, at least one first stereoscopic electrode and a display medium layer. The sub-pixel is defined by a color filter and a black matrix disposed adjacently to the color filter. The reflecting layer is located beneath the sub-pixel. The first stereoscopic electrode is located beneath the black matrix. The width of the first stereoscopic electrode is less than the width of the black matrix. The display medium layer is located between the sub-pixel and the reflecting layer. The height of the first stereoscopic electrode is greater than half of the thickness of the display medium layer.

A total internal reflection display includes a sub-pixel, a reflecting layer, at least one first stereoscopic electrode and a display medium layer. The sub-pixel is defined by a color filter and a black matrix disposed adjacently to the color filter. The reflecting layer is located beneath the sub-pixel. The first stereoscopic electrode is located beneath the black matrix. The width of the first stereoscopic electrode is less than the width of the black matrix. The display medium layer is located between the sub-pixel and the reflecting layer. The height of the first stereoscopic electrode is greater than half of the thickness of the display medium layer.

A display substrate, including: a base substrate; a plurality of gate lines and a plurality of data lines that intersect to surround a plurality of pixels; wherein each pixel includes a first thin film transistor, a second thin film transistor and a pixel electrode. A first electrode of the first thin film transistor is electrically connected to a pixel conductive layer of the pixel electrode, a second electrode of the first thin film transistor is electrically connected to a first electrode of the second thin film transistor, and a second electrode of the second thin film transistor is electrically connected to the data line. An orthographic projection of a combination of the second electrode of the first thin film transistor and the first electrode of the second thin film transistor on the base substrate at least partially overlaps with an orthographic projection of the pixel conductive layer on the base substrate.