The present application discloses a method for measuring critical dimension. The method for measuring critical dimension includes providing a substrate; forming a resist layer over the substrate; monitoring a volatile byproduct evolved from the resist layer to obtain a first amount of the volatile byproduct; exposing the resist layer to a radiation source; heating the resist layer; monitoring the volatile byproduct evolved from the resist layer to obtain a second amount of the volatile byproduct; and deducting the critical dimension according to a difference between the first amount of the volatile byproduct and the second amount of the volatile byproduct.

The present application discloses a method for measuring critical dimension. The method for measuring critical dimension includes providing a substrate; forming a resist layer over the substrate; monitoring a volatile byproduct evolved from the resist layer to obtain a first amount of the volatile byproduct; exposing the resist layer to a radiation source; heating the resist layer; monitoring the volatile byproduct evolved from the resist layer to obtain a second amount of the volatile byproduct; and deducting the critical dimension according to a difference between the first amount of the volatile byproduct and the second amount of the volatile byproduct.

An inspection tool comprises an imaging system configured to image a portion of a semiconductor substrate. The inspection tool may further comprise an image analysis system configured to obtain an image of a structure on the semiconductor substrate from the imaging system, encode the image of the structure into a latent space thereby forming a first encoding. the image analysis system may subtract an artifact vector, representative of an artifact in the image, from the encoding thereby forming a second encoding; and decode the second encoding to obtain a decoded image.

A system and methods for OCD metrology are provided including receiving reference parameters, receiving multiple sets of measured scatterometric data, and receiving an optical model designed to generate one or more sets of model scatterometric data according to a set of pattern parameters, and training a machine learning model by applying, during the training, target features including the reference parameters, and by applying input features including the sets of measured scatterometric data and the sets of model scatterometric data, such that the trained machine learning model estimates new wafer pattern parameters from subsequently sets of measured scatterometric data.

A data processing device for detecting defects in sample image data generated by a charged particle assessment system, the device comprising: a first processing module configured to receive a sample image datastream from the charged particle assessment system, the sample image datastream comprising an ordered series of data points representing an image of the sample, and to apply a first defect detection test to select a subset of the sample image datastream as first selected data, wherein the first defect detection test is a localised test which is performed in parallel with receipt of the sample image datastream; and a second processing module configured to receive the first selected data and to apply a second defect detection test to select a subset of the first selected data as second selected data.

Methods and systems for IC photomask patterning are described. In some embodiments, a method includes inserting a dummy region in an IC design layout, the IC design layout includes an active region, and the active region and the dummy region is separated by a first distance. The method further includes performing one or more operations on the IC design layout, and the active region and the dummy region is separated by a second distance substantially less than the first distance. The method further includes performing a dummy region size reduction on the IC design layout to increase the second distance to a third distance substantially greater than the second distance, and the third distance is substantially greater than a minimum feature size to be patterned by a photolithography tool. The method further includes forming a photomask using the IC design layout.

A critical dimension uniformity control method is provided. The method includes gathering a first CDU by a first critical dimension from a first wafer after being processed by a first surface process. The method includes determining a first calibration process based on the first CDU. The determining includes an intra dose correction step for correcting reticle-dependent deviation, a thru-slit dose sensitivity correction step for correcting time-dependent deviation, and an inter dose correction step for correcting process-dependent deviation. The method includes calibrating the first surface process by the first calibration process to determine a second surface process different from the first surface process.

A metrology system is disclosed. In one embodiment, the metrology system includes a controller communicatively coupled to a reference metrology tool and an optical metrology tool, the controller including one or more processors configured to: generate a geometric model for determining a profile of a test HAR structure from metrology data from a reference metrology tool; generate a material model for determining one or more material parameters of a test HAR structure from metrology data from the optical metrology tool; form a composite model from the geometric model and the material model; measure at least one additional test HAR structure with the optical metrology tool; and determine a profile of the at least one additional test HAR structure based on the composite model and metrology data from the optical metrology tool associated with the at least one HAR test structure.

Computer-implemented methods of optimizing a process simulation model that predicts a result of a semiconductor device fabrication operation to process parameter values characterizing the semiconductor device fabrication operation are disclosed. The methods involve generating cost values using a computationally predicted result of the semiconductor device fabrication operation and a metrology result produced, at least in part, by performing the semiconductor device fabrication operation in a reaction chamber operating under a set of fixed process parameter values. The determination of the parameters of the process simulation model may employ pre-process profiles, via optimization of the resultant post-process profiles of the parameters against profile metrology results. Cost values for, e.g., optical scatterometry, scanning electron microscopy and transmission electron microscopy may be used to guide optimization.

A system and methods for OCD metrology are provided including receiving training data for training an OCD machine learning (ML) model, including multiple pairs of corresponding sets of scatterometric data and reference parameters. For each of the pairs, one or more corresponding outlier metrics are by calculated and corresponding outlier thresholds are applied whether a given pair is an outlier pair. The OCD MIL model is then trained with the training data less the outlier pairs.