G03F7/70633

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME
20230010665 · 2023-01-12 · ·

A semiconductor structure includes vertical conductive features disposed over a substrate, and horizontal conductive features disposed over the vertical conductive features. The horizontal conductive features include first and second conductive lines respectively electrically connected to the first and second vertical conductive features, a first conductive segment disposed between the first vertical conductive feature and the second conductive line, and a second conductive segment disposed between the first conductive line and the second vertical conductive feature. The first conductive segment is electrically isolated from the vertical conductive features. The second conductive segment is electrically isolated from the vertical conductive features.

LITHOGRAPHIC APPARATUS, MULTI-WAVELENGTH PHASE-MODULATED SCANNING METROLOGY SYSTEM AND METHOD

A metrology system includes a radiation source, first, second, and third optical systems, and a processor. The first optical system splits the radiation into first and second beams of radiation and impart one or more phase differences between the first and second beams. The second optical system directs the first and second beams toward a target structure to produce first and second scattered beams of radiation. The third optical system interferes the first and second scattered beams at an imaging detector. The imaging detector generates a detection signal based on the interfered first and second scattered beams. The metrology system modulates one or more phase differences of the first and second scattered beams based on the imparted one or more phase differences. The processor analyzes the detection signal to determine a property of the target structure based on at least the modulated one or more phase differences.

LITHOGRAPHIC APPARATUS, METROLOGY SYSTEMS, ILLUMINATION SWITCHES AND METHODS THEREOF

A system includes an illumination system, an optical element, a switching element and a detector. The illumination system includes a broadband light source that generates a beam of radiation. The dispersive optical element receives the beam of radiation and generates a plurality of light beams having a narrower bandwidth than the broadband light source. The optical switch receives the plurality of light 5 beams and transmits each one of the plurality of light beams to a respective one of a plurality of alignment sensor of a sensor array. The detector receives radiation returning from the sensor array and to generate a measurement signal based on the received radiation.

METHOD FOR OVERLAY ERROR CORRECTION
20230213874 · 2023-07-06 ·

The present disclosure provides a method for overlay error correction. The method includes: obtaining an overlay error based on a lower-layer pattern and an upper-layer pattern of a wafer, wherein the lower-layer pattern is obtained by first fabrication equipment through which the wafer passes, and the upper-layer pattern is obtained by exposure equipment; generating a corrected overlay error based on the overlay error and fabrication processes performed on the wafer after the first fabrication equipment and prior to the exposure equipment; and adjusting the exposure equipment based on the corrected overlay error.

METHOD FOR OVERLAY ERROR CORRECTION AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE STRUCTURE WITH OVERLAY MARKS
20230213873 · 2023-07-06 ·

A method for overlay error correction includes generating a first overlay error based on a first overlay mark, wherein the first overlay error is indicative of a misalignment between a lower pattern and an upper pattern of the first overlay mark. The method also includes generating a second overlay error based on a second overlay mark, in response to an abnormal of the first overlay error is detected. The method further includes determining whether the abnormal of the first overlay error is caused by the misalignment between the lower pattern and the upper pattern depending on the second overlay error.

MARK FOR OVERLAY MEASUREMENT
20230213872 · 2023-07-06 ·

The present disclosure provides a mark for overlay error measurement. The mark includes a first pattern and a second pattern. The first pattern is disposed on a substrate and at a first horizontal level. The first pattern includes a plurality of first sub-patterns and a plurality of second sub-patterns. The first sub-patterns extend along a first direction and are arranged along a second direction different from the first direction. The second sub-patterns are arranged along the second direction, wherein a profile of each of the plurality of first sub-patterns is different from a profile of each of the plurality of second sub-patterns. The second pattern is disposed at a second horizontal level different from the first horizontal level.

SCANNING OVERLAY METROLOGY USING OVERLAY TARGETS HAVING MULTIPLE SPATIAL FREQUENCIES
20230213875 · 2023-07-06 ·

An overlay metrology system may include an illumination source and illumination optics to illuminate an overlay target on a sample with illumination from the illumination source as the sample is in motion with respect to the illumination from the illumination source in accordance with a measurement recipe. The overlay target may include one or more cells, where a single cell is suitable for measurement along a particular direction. Such a cell may include two or more gratings with different pitches. Further, the system may include two or more photodetectors, each configured to capture three diffraction lobes from the two or more grating structures. The system may further include a controller to determine an overlay measurement associated with each cell of the overlay target.

Three dimensional integrated semiconductor architecture having alignment marks provided in a carrier substrate

Provided is a semiconductor architecture including a carrier substrate, alignment marks provided in the carrier substrate, the alignment marks being provided from a first surface of the carrier substrate to a second surface of the carrier substrate, a first semiconductor device provided on the first surface of the carrier substrate based on the alignment marks, a second semiconductor device provided on the second surface of the carrier substrate based on the alignment marks and aligned with the first semiconductor device.

Measurement apparatus, lithography apparatus and article manufacturing method
11693328 · 2023-07-04 · ·

The present invention provides a measurement apparatus for measuring a position of a first pattern and a position of a second pattern provided in a target object, the apparatus including an image capturing unit including a plurality of pixels which detect light from the first pattern and light from the second pattern, and configured to form an image capturing region used to capture the first pattern and the second pattern by the plurality of pixels, and a control unit configured to adjust the image capturing unit such that a relative ratio of an intensity of a detection signal of the first pattern generated based on an output from a first image capturing region and an intensity of a detection signal of the second pattern generated based on an output from a second image capturing region falls within an allowable range.

OVERLAY DESIGN FOR ELECTRON BEAM AND SCATTEROMETRY OVERLAY MEASUREMENTS

Combined electron beam overlay and scatterometry overlay targets include first and second periodic structures with gratings. Gratings in the second periodic structure can be positioned under the gratings of the first periodic structure or can be positioned between the gratings of the first periodic structure. These overlay targets can be used in semiconductor manufacturing.