A method and associated computer program for predicting an electrical characteristic of a substrate subject to a process. The method includes determining a sensitivity of the electrical characteristic to a process characteristic, based on analysis of electrical metrology data including electrical characteristic measurements from previously processed substrates and of process metrology data including measurements of at least one parameter related to the process characteristic measured from the previously processed substrates; obtaining process metrology data related to the substrate describing the at least one parameter; and predicting the electrical characteristic of the substrate based on the sensitivity and the process metrology data.

A method and associated computer program for predicting an electrical characteristic of a substrate subject to a process. The method includes determining a sensitivity of the electrical characteristic to a process characteristic, based on analysis of electrical metrology data including electrical characteristic measurements from previously processed substrates and of process metrology data including measurements of at least one parameter related to the process characteristic measured from the previously processed substrates; obtaining process metrology data related to the substrate describing the at least one parameter; and predicting the electrical characteristic of the substrate based on the sensitivity and the process metrology data.

The wafer comprises a first line in a first layer of the wafer. The first line has a first terminal connected to the first line. The wafer comprises a second line in the first layer of the wafer. The second line has a second terminal connected to the second line. The second terminal has a probe connected to apply a voltage ramp. The wafer comprises a third line in the first layer of the wafer. The third line has a terminal connected to the third line.

A method for detecting overlay misalignment of a semiconductor device uses a test structure that includes a sensor structure and a via-chain structure. The sensor structure is disposed in a first layer on a semiconductor substrate and includes a plurality of first conductive lines extending in a first direction. Each first conductive line is separated from an adjacent first conductive line in a second direction by a first space. The via-chain structure is in a second layer above the first layer and between the first layer and the second layer. The via-chain structure includes at least one second conductive line disposed in the second layer and at least one via electrically connected to each second conductive line and extending toward the first layer. The at least one via is disposed in the first space between the adjacent first conductive lines of the sensor structure.

A method of determining a characteristic of one or more processes for manufacturing features on a substrate, the method including: obtaining image data of a plurality of features on a least part of at least one region on a substrate; using the image data to obtain measured data of one or more dimensions of each of at least some of the plurality of features; determining a statistical parameter that is dependent on the variation of the measured data of one or more dimensions of each of at least some of the plurality of features; determining a probability of defective manufacture of features in dependence on a determined number of defective features in the image data; and determining the characteristic of the one or more processes to have the probability of defective manufacture of features and the statistical parameter.

A method for detecting overlay misalignment of a semiconductor device uses a test structure that includes a sensor structure and a via-chain structure. The sensor structure is disposed in a first layer on a semiconductor substrate and includes a plurality of first conductive lines extending in a first direction. Each first conductive line is separated from an adjacent first conductive line in a second direction by a first space. The via-chain structure is in a second layer above the first layer and between the first layer and the second layer. The via-chain structure includes at least one second conductive line disposed in the second layer and at least one via electrically connected to each second conductive line and extending toward the first layer. The at least one via is disposed in the first space between the adjacent first conductive lines of the sensor structure.

A set of test key layout including multiple test keys and method of monitoring layout pattern misalignments using the test keys is provided. Each test key is composed of a testing electrode, an operating voltage (V.sub.dd) line and a grounding voltage (V.sub.ss) line, wherein the patterns of test keys are defined by an overlapped portion of a first exposure pattern and a second exposure pattern, and the position of testing electrode is shifted sequentially in one direction in order of the test keys.

A method and associated computer program for predicting an electrical characteristic of a substrate subject to a process. The method includes determining a sensitivity of the electrical characteristic to a process characteristic, based on analysis of electrical metrology data including electrical characteristic measurements from previously processed substrates and of process metrology data including measurements of at least one parameter related to the process characteristic measured from the previously processed substrates; obtaining process metrology data related to the substrate describing the at least one parameter; and predicting the electrical characteristic of the substrate based on the sensitivity and the process metrology data.

A method for determining a spatially varying process offset for a lithographic process, the spatially varying process offset (MTD) varying over a substrate subject to the lithographic process to form one or more structures thereon. The method includes obtaining a trained model (MOD), having been trained to predict first metrology data based on second metrology data, wherein the first metrology data (OV) is spatially varying metrology data which relates to a first type of measurement of the one or more structures being a measure of yield and the second metrology data (PB) is spatially varying metrology data which relates to a second type of measurement of the one or more structures and correlates with the first metrology data; and using the model to obtain the spatially varying process offset (MTD).

A method of determining a characteristic of one or more processes for manufacturing features on a substrate, the method including: obtaining image data of a plurality of features on a least part of at least one region on a substrate; using the image data to obtain measured data of one or more dimensions of each of at least some of the plurality of features; determining a statistical parameter that is dependent on the variation of the measured data of one or more dimensions of each of at least some of the plurality of features; determining a probability of defective manufacture of features in dependence on a determined number of defective features in the image data; and determining the characteristic of the one or more processes to have the probability of defective manufacture of features and the statistical parameter.