The present disclosure provides a measurement mark, a measurement layout, and a semiconductor structure measurement method. A measurement mark includes a first pattern, a second pattern, and a third pattern, the first pattern includes multiple first marks extending in a first direction and arranged in parallel at intervals in a second direction, the second pattern includes multiple second marks arranged at intervals in a staggered manner, and the third pattern includes multiple third marks arranged at intervals in a staggered manner; in projection of the measurement mark on the substrate, projection of the second mark separates projection of the first mark in the first direction; projection of the second pattern does not overlap with projection of the third pattern, and there is an offset distance between the projection of the third pattern and the projection of the second pattern in a third direction.

A photolithography exposure of a photoresist coating on a semiconductor wafer uses an optical projection system to form a latent image. The photolithography exposure further uses a mask with a set of multiple pattern focus (MPF) marks. Each MPF mark of includes features having different critical dimension (CD) sizes. The latent image is developed to form a developed photoresist pattern. Dimension sizes are measured of features of the developed photoresist pattern corresponding to the features of the MPF marks having different CD sizes. A spatial focus map of the photolithography exposure is constructed based on the measured dimension sizes. To determine the focal distance at an MPF mark, ratios or differences may be determined between the measured dimension sizes corresponding to the features of the MPF marks having different CD sizes, and the focal distance at the location of the MFP mark constructed based on the determined ratios or differences.

The present disclosure provides a mark for overlay error measurement. The mark includes a first pattern and a second pattern. The first pattern is disposed on a substrate and at a first horizontal level. The first pattern includes a plurality of first sub-patterns and a plurality of second sub-patterns. The first sub-patterns extend along a first direction and are arranged along a second direction different from the first direction. The second sub-patterns are arranged along the second direction, wherein a profile of each of the plurality of first sub-patterns is different from a profile of each of the plurality of second sub-patterns. The second pattern is disposed at a second horizontal level different from the first horizontal level.

An overlay metrology system may include an illumination source and illumination optics to illuminate an overlay target on a sample with illumination from the illumination source as the sample is in motion with respect to the illumination from the illumination source in accordance with a measurement recipe. The overlay target may include one or more cells, where a single cell is suitable for measurement along a particular direction. Such a cell may include two or more gratings with different pitches. Further, the system may include two or more photodetectors, each configured to capture three diffraction lobes from the two or more grating structures. The system may further include a controller to determine an overlay measurement associated with each cell of the overlay target.

The present invention provides a measurement apparatus for measuring a position of a first pattern and a position of a second pattern provided in a target object, the apparatus including an image capturing unit including a plurality of pixels which detect light from the first pattern and light from the second pattern, and configured to form an image capturing region used to capture the first pattern and the second pattern by the plurality of pixels, and a control unit configured to adjust the image capturing unit such that a relative ratio of an intensity of a detection signal of the first pattern generated based on an output from a first image capturing region and an intensity of a detection signal of the second pattern generated based on an output from a second image capturing region falls within an allowable range.

Combined electron beam overlay and scatterometry overlay targets include first and second periodic structures with gratings. Gratings in the second periodic structure can be positioned under the gratings of the first periodic structure or can be positioned between the gratings of the first periodic structure. These overlay targets can be used in semiconductor manufacturing.

Electron beam overlay targets and method of performing overlay measurements on a target using a semiconductor metrology tool are provided. One target includes a plurality of electron beam overlay elements and a plurality of two-dimensional elements that provide at least one two-dimensional imaging. The plurality of two dimensional elements are an array of evenly-spaced polygonal gratings across at least three rows and at least three columns. Another target includes a plurality of electron beam overlay elements and a plurality of AIMid elements. Each of the electron beam overlay elements includes at least two gratings that are overlaid at a perpendicular orientation to each other. The plurality of AIMid elements includes at least two gratings that are overlaid at a perpendicular orientation to each other.

Metrology methods and targets are provided for reducing or eliminating a difference between a device pattern position and a target pattern position while maintaining target printability, process compatibility and optical contrast—in both imaging and scatterometry metrology. Pattern placement discrepancies may be reduced by using sub-resolved assist features in the mask design which have a same periodicity (fine pitch) as the periodic structure and/or by calibrating the measurement results using PPE (pattern placement error) correction factors derived by applying learning procedures to specific calibration terms, in measurements and/or simulations. Metrology targets are disclosed with multiple periodic structures at the same layer (in addition to regular target structures), e.g., in one or two layers, which are used to calibrate and remove PPE, especially when related to asymmetric effects such as scanner aberrations, off-axis illumination and other error sources.

A method of manufacturing a semiconductor device includes: forming a first outer box and a second outer box on a wafer, providing a photoresist layer on the wafer; and by removing a portion of the photoresist layer, forming a photoresist pattern including a first opening and a second opening that are horizontally apart from each other, wherein the first opening defines a first inner box superimposed on the first outer box in a plan view, the second opening defines a second inner box superimposed on the second outer box in the plan view, and a horizontal distance between the first opening and the second opening is about 150 μm to about 400 μm.

In a dark-field metrology method using a small target, a characteristic of an image of the target, obtained using a single diffraction order, is determined by fitting a combination fit function to the measured image. The combination fit function includes terms selected to represent aspects of the physical sensor and the target. Some coefficients of the combination fit function are determined based on parameters of the measurement process and/or target. In an embodiment the combination fit function includes jinc functions representing the point spread function of a pupil stop in the imaging system.