A metrology method comprising: performing a first exposure on a substrate to form a first patterned layer including a plurality of first target units, each first target unit comprising a first target feature; performing a second exposure on the substrate to form a second patterned layer comprising second target units overlying respective ones of the first target units, each of the second target units having a second target feature, wherein ones of the second target units have the second target feature positioned at respectively different offsets relative to a reference position: imaging the second target units overlaid on the first target units; and determining an edge placement error based on positions of edges of second target features in second target units relative to edges of the first target feature of the underlying first target unit.

The present application provides a method for improving overlay metrology accuracy of self-aligned multiple patterning, overlay metrology pattern comprising a front layer pattern and a current layer pattern, the front layer pattern comprising a plurality of first grating structures overlaid on the periphery of the current layer pattern, the first grating structure being composed of a plurality of repeatedly arranged strip elements; segmenting the strip element in the first grating structure, so that each of the strip elements forms a sub-grating structure comprising a plurality of repeatedly arranged strip structures; forming a plurality of repeatedly arranged core structures corresponding to the plurality of repeatedly arranged strip structures; form a gate structure comprising a plurality of repeatedly arranged fin structures; removing two outermost fin structures of the gate structure; the gate structure and the current layer pattern structure together forming an overlay metrology structure.

A focus-sensitive metrology target may be formed and read-out by a fabrication tool. A resulting overlay signal may be translated into a focus offset by comparison to a previously-determined calibration curve. One or more translated signals may be fed back to the fabrication tool for focus correction or used for prediction of on-device overlay (correction of overlay metrology results). In one embodiment, focus and overlay may be measured using a single target, where one portion of the target is formed on a first layer and includes a focus-sensitive design, and where another portion of the target is formed on a second layer and includes a relatively less focus-sensitive design. In some embodiments, a relative difference in focus response may be used to estimate an impact of focus error on device overlay and calculate non-zero offset contributions.

A grating for use in metrology including a periodic structure including a plurality of units having a pitch P, at least one unit of the plurality of units including at least a first periodic sub-structure having a first sub-pitch P1 smaller than the pitch P, and at least a second periodic sub-structure arranged along-side and separated from the first periodic sub-structure within the at least one unit and having a second sub-pitch P2 smaller than the pitch P and different from the first sub-pitch P1, P1 and P2 being selected to yield at least one Moir pitch P.sub.m=P1.Math.P2/(P2−P1), the pitch P being an integer multiple of the first sub-pitch P and of the second sub-pitch P2.

A method for applying a deposition model in a semiconductor manufacturing process. The method includes predicting a deposition profile of a substrate using the deposition model; and using the predicted deposition profile to enhance a metrology target design. The deposition model can be calibrated using experimental cross-section profile information from a layer of a physical substrate. In some embodiments, the deposition model is a machine-learning model, and calibrating the deposition model includes training the machine-learning model. The metrology target design may include an alignment metrology target design or an overlay metrology target design, for example.

A method, system and computer program product for determination of a metrology target design, comprising generating a first candidate target design for a selected design type compatible with one or more metrology tools or and a set of boundaries for a simulation range Measurement of the first target design with the one or more metrology tools within the boundaries of the simulation range is simulated for two or more measurement settings to generate one or more performance metrics. Simulating the measurement takes into account layer properties of one or more layers in a stack profile. The optimal design is determined from at least the performance metrics based on one or more selection criteria and then sent or stored.

According to one embodiment, a measurement method includes generating mark position information, determining at least one of a first arrangement pattern or a second arrangement pattern, and calculating displacement between a first member and a second member. The mark position information is generated after the second member is formed on the first member, and indicates a relative positional relationship between a first alignment mark formed on the first member and including bright portions and dark portions, and a second alignment mark formed on the second member and including the bright portions and the dark portions. The first arrangement pattern indicates an arrangement pattern of bright portions and dark portions of the first alignment mark. The second arrangement pattern indicates an arrangement pattern of the bright portions and the dark portions of the second alignment mark. The first arrangement pattern is determined on the basis of captured data of a reference mark formed in a region different from the region where the first alignment mark is formed and the region where the second alignment mark is formed. The displacement is calculated on the basis of the mark position information and at least one of the first arrangement pattern or the second arrangement pattern.

A semiconductor structure, a method for manufacturing the same and a memory are provided. The semiconductor structure at least includes two photolithography layers which are arranged in sequence and at least one blocking layer. Each photolithography layer includes a functional pattern and an overlay mark, and the photolithography layers include a first photolithography layer and a second photolithography layer. The first photolithography layer includes a first functional pattern and a first overlay mark, and the second photolithography layer includes a second functional pattern and a second overlay mark; and at least one blocking layer. The blocking layer is located between the first functional pattern and the second functional pattern, and a vertical distance between the first functional pattern and the second functional pattern is greater than a vertical distance between the first and second overlay marks, in a stacking direction of the photolithography layers.

An overlay measurement method for accurately measuring and correcting an overlay in an environment in which a deep ultraviolet (DUV) apparatus and an extreme ultraviolet (EUV) apparatus are used together, a semiconductor device manufacturing method using the overlay measurement method, and an overlay measurement apparatus are provided. The overlay measurement method includes performing an absolute measurement of a position of an overlay mark of at least one of a plurality of layers, based on a fixed position, wherein an exposure process is performed on a first layer of the plurality of layers by using the DUV apparatus, and an exposure process is performed on an nth layer of the plurality of layers, which is an uppermost layer of the plurality of layers, by using the EUV apparatus.

Metrology targets and methods are provided, which comprise at least two overlapping structures configured to be measurable in a mutually exclusive manner at least at two different corresponding optical conditions. The targets may be single cell targets which are measured at different optical conditions which enable independent measurements of the different layers of the target. Accordingly, the targets may be designed to be very small, and be located in-die for providing accurate metrology measured of complex devices.