Embodiments described herein may be related to apparatuses, processes, and techniques related to using full stack overlay cell (FSOL) targets within lithography masks and on fabricated layers of a substrate in order to align or to assess the alignment of fabricated layers of the substrate during the substrate manufacturing process. Other embodiments may be described and/or claimed.

A test structure and method of its manufacture are presented for use in metrology measurements of a sample pattern. The test structure comprises a test pattern comprising a portion of the sample pattern including at least one selected feature and a blocking layer at least partially covering regions of the test structure adjacent to the at least one selected region

A metrology target includes a first target structure set having one or more first target structures formed within at least one of a first working zone or a second working zone of a sample. The metrology target includes a second target structure set having one or more second target structures formed within at least one of the first working zone or the second working zone. The first working zone may include a center of symmetry that overlaps with a center of symmetry of the second working zone when an overlay error of one or more layers of the sample is not present. The metrology target may additionally include a third target structure set, a fourth target structure set, or a fifth target structure set.

The present disclosure provides an overlay mark, an overlay error measurement method for a wafer, and a wafer stacking method. The overlay mark includes a first overlay mark disposed on a first layer, and a second overlay mark disposed on a second layer. The first layer and the second layer are stacked. The first overlay mark includes at least one first overlay sub-mark, and each of the at least one first overlay sub-mark is circular in shape. The second overlay mark includes a second overlay sub-mark, and the second overlay sub-mark is in a center-symmetrical shape including a plurality of linear graphics.

Apparatuses and methods of overlay measurement are disclosed. An example apparatus includes: a substrate comprising first material; a first layer comprising second material disposed on a surface of in the substrate; a first alignment pattern including third material disposed in the first layer; and a second layer above the first layer including a second alignment pattern. A difference between refractive indexes of the second material and the third material is greater than a difference between refractive indexes of the first material and the third material.

A method for semiconductor metrology includes depositing a first film layer on a semiconductor substrate and a second film layer overlying the first film layer. The first and second film layers are patterned to create an overlay target having a specified geometrical form by using a projection system having a predefined resolution limit to project optical radiation onto the semiconductor substrate through at least one mask. The mask contains target features having target feature dimensions no less than the predefined resolution limit in an arrangement corresponding to the specified geometrical form of the overlay target and assist features interleaved with the target features and having at least one assist feature dimension that is less than the predefined resolution limit.

A method may include forming a first grating and a second grating, disposed in a region of vertical overlap of the first and second gratings on different levels, respectively, having substantially the same pitch, and inclined with respect to each other, such that a bias value between the first and second gratings is changed along a length direction of the first and second gratings, using a lithography process. A method may include emitting a beam to the first and second gratings; and obtaining trend information associated with a diffracted beam from an image pattern of a beam from the first and second gratings, using the emitted beam, in which the trend information may concern changes in the intensity of the diffracted beam according to the bias value. An overlay error in at least one grating may be determined based on the trend information and an intensity of a diffracted beam.

A method including performing a simulation to evaluate a plurality of metrology targets and/or a plurality of metrology recipes used to measure a metrology target, identifying one or more metrology targets and/or metrology recipes from the evaluated plurality of metrology targets and/or metrology recipes, receiving measurement data of the one or more identified metrology targets and/or metrology recipes, and using the measurement data to tune a metrology target parameter or metrology recipe parameter.

Aspects of the present disclosure provide a method of aligning a wafer pattern. For example, the method can include providing a wafer having a reference pattern located below a front side of the wafer, and directing a light beam to the wafer. The method can further include identifying at least one of power and a wavelength of the light beam such that the light beam is capable of passing through the wafer and reaching the reference pattern, or identifying at least one of power and a wavelength of the light beam based on at least one of a material of the wafer and a depth of the reference pattern below the front side of the wafer. The method can further include using the light beam to image the reference pattern.

A method for improving a design of a patterning device. The method includes (i) obtaining mask points of a design of a mask feature, wherein the mask feature corresponds to a target feature in a target pattern to be printed on a substrate; and (ii) adjusting locations of the mask points to generate a modified design of the mask feature based on the adjusted mask points.