A measuring device includes a light source that irradiates a measurement spot on a wafer formed with memory holes and slits with a multi-wavelength light, a first imaging unit that acquires a first pupil plane intensity distribution image of reflected light from the measurement spot, a second imaging unit that acquires a second pupil plane intensity distribution image of the reflected light, and a detection unit that analyzes the second pupil plane intensity distribution image to measure overlay. The measuring device includes an overlay analysis unit that acquires the first and second pupil plane intensity distribution images while moving a position of the measurement spot and selects a measurement spot not including the slit based on the first pupil plane intensity distribution image, and uses the overlay obtained by analyzing the second pupil plane intensity distribution image of the selected measurement spot as the overlay of the memory hole and a slit.

A method may include, but is not limited to, receiving a measurement including a metrology parameter for a layer of a metrology target and an alignment mark from an overlay metrology tool prior to a lithography process; deriving a merit figure from the metrology parameter and the alignment mark; deriving a correction factor from the merit figure; providing the correction factor to the lithography process via a feed forward process; receiving an additional measurement including an additional metrology parameter for the layer and an additional layer from an additional overlay metrology tool after the lithography process; deriving an adjustment from the additional metrology parameter; and providing the adjustment to the lithography process via a feedback process.

Increasingly, metrology systems are integrated within the lithographic apparatuses, to provide integrated metrology within the lithographic process. However, this integration can result in a throughput or productivity impact of the whole lithographic apparatus which can be difficult to predict. It is therefore proposed to provide a simulation model which is operable to acquire throughput information associated with a throughput of a plurality of substrates within a lithographic apparatus, said throughput information comprising a throughput parameter, predict, using a throughput simulator the throughput using the throughput parameter as an input parameter. The throughput simulator may be calibrated using the acquired throughput information. The impact of at least one change of a throughput parameter on the throughput of the lithographic apparatus may be predicted using the throughput simulator.

Methods and corresponding metrology modules and systems, which measure metrology parameter(s) of a previous layer of a metrology target and/or an alignment mark, prior to producing a current layer of the metrology target, derive merit figure(s) from the measured metrology parameter(s) to indicate an inaccuracy, and compensate for the inaccuracy to enhance subsequent overlay measurements of the metrology target. In an example embodiment, methods and corresponding metrology modules and systems use stand-alone metrology tool(s) and track-integrated metrology tool(s) at distinct measurement patterns to address separately different aspects of variation among wafers.

A metrology system may receive design data including a layout of fabricated instances of a structure on a sample. The system may further receive detection signals from the metrology tool associated within a field of view including multiple of the fabricated instances of the structure. The system may further generate design-assisted composite data for the structure by combining detection signals from one or more common features of the structure associated with the fabricated instances of the structure within the field of view using the design data. The system may further generate one or more metrology measurements of the structure based on the design-assisted composite data.

Methods and systems for selecting measurement locations on a wafer for subsequent detailed measurements employed to characterize the entire wafer are described herein. High throughput measurements are performed at a relatively large number of measurement sites on a wafer. The measurement signals are transformed to a new mathematical basis and reduced to a significantly smaller dimension in the new basis. A set of representative measurement sites is selected based on analyzing variation of the high throughput measurement signals. In some embodiments, the spectra are subdivided into a set of different groups. The spectra are grouped together to minimize variance within each group. Furthermore, a die location is selected that is representative of the variance exhibited by the die in each group. A spectrum of a measurement site and corresponding wafer location is selected to correspond most closely to the center point of each cluster.

A wafer metrology system including a dynamic sampling scheme configured to optimize a sampling rate for measurement of process wafers in an IC fabrication flow based on process capability index data as well as measurement history data. For a stable process, the process wafers may be sampled at a lower rate without negatively affecting quality control.

Embodiments of this invention provide a measurement map configuration method and apparatus. A wafer to be inspected is provided. The wafer includes a plurality of inspection marks. A first inspection result is obtained based on a first set of inspection marks. A second set of inspection marks is selected based on a preset rule. The second set of inspection marks is less than the first set of inspection marks. A second inspection result is obtained based on the second set of inspection marks. If an overlay accuracy of the second inspection result matches an overlay accuracy the first inspection result, a measurement map for the wafer is set based on target inspection marks. The target inspection marks are the second set of inspection marks of the measurement map.

Generating an alignment signal for alignment of features in a layer of a substrate as part of a semiconductor manufacturing process is described. The present systems and methods can be faster and/or generate more information than typical methods for generating alignment signals because they utilize one or more existing structures in a patterned semiconductor wafer instead of a dedicated alignment structure. A feature (not a dedicated alignment mark) of the patterned semiconductor wafer is continuously scanned, where the scanning includes: continuously irradiating the feature with radiation; and continuously detecting reflected radiation from the feature. The scanning is performed perpendicular to the feature, along one side of the feature, or along both sides of the feature.

A system and methods for OCD metrology are provided including receiving training data for training an OCD machine learning (ML) model, the training data measured from multiple wafers and including multiple pairs of corresponding input and label datasets obtained from each respective wafer. The input dataset of each pair includes multiple scatterometric datasets, measured at multiple respective locations defined by a first map. The label dataset of each pair includes one or more critical dimension (CD) parameters of respective locations defined by a second map, the second map including at least one location not in the first map. The OCD ML model is then applied to a new set of scatterometric datasets, measured from locations of a new wafer, according to the first map, to generate predicted CD parameters of locations of the second map on the new wafer.