Provided are an overlay correction method for effectively correcting an overlay due to degradation of a wafer table, and an exposure method and a semiconductor device manufacturing method, which include the overlay correction method, wherein the overlay correction method includes acquiring leveling data regarding a wafer, converting the leveling data into overlay data, splitting a shot into sub-shots via shot size split, extracting a model for each sub-shot from the overlay data, and correcting an overlay parameter of exposure equipment on the basis of the model for each sub-shot, wherein the correction of the overlay parameter is applied in real time to an exposure process for the wafer in a feedforward method.

Lithograph mask generation processes that apply optical lithography simulation on a mask image to generate a resist image, perform curvilinear design retargeting on the resist image, determine a gradient from the generated resist image and a configured target resist image, and apply morphological operators and the gradient to update the mask image.

A method of manufacturing includes receiving a design layout of a target pattern, generating an optical proximity correction (OPC) model the design layout, obtaining an optical proximity corrected (OPCed) design layout by a simulation based on the OPC model, and forming at least one of a mask and a semiconductor device using the OPCed design layout, wherein the generating of the OPC model includes obtaining a vectorized first kernel by vectorizing a first kernel, preparing a first input image by using the design layout of the target pattern, obtaining a vectorized first input image by vectorizing the first input image, obtaining a first rotation image by rotating the vectorized first input image in a first direction, extracting a second kernel by calculating a dot product of the vectorized first kernel and the first rotation image, obtaining a second rotation image by symmetrizing the first rotation image, and extracting a fourth kernel by calculating a dot product of the vectorized first kernel and the second rotation image. The simulation is performed by using the second kernel.

Disclosed is a method of determining a performance parameter or a parameter derived therefrom, the performance parameter being associated with a performance of a lithographic process for forming one or more structures on a substrate subject to the lithographic process. The method comprises obtaining a probability description distribution comprising a plurality of probability descriptions of the performance parameter, each probability description corresponding to a different position on the substrate and decomposing each probability description into a plurality of component probability descriptions to obtain a plurality of component probability description distributions. A component across-substrate-area model is determined for each of said plurality of component probability descriptions, which models its respective component probability description across a substrate area; and a value for said performance parameter or parameter derived therefrom is determined based on the component across-substrate-area models.

Methods, computer programs, and systems are disclosed, with one method including characterizing a depth variation of a predicted result within a feature of a pattern from a lithography simulation. The method evaluates the depth variation characterization and selects patterns or gauges based on the depth variation evaluation. In some embodiments, the evaluating can be based on an aerial image (AI) depth sensitivity having the depth variation.

A metrology system includes an illumination source generating illumination beams. Illumination optics direct the beams to a sample surface at non-zero incidence angles. Detectors collect light from the sample surface, with collection optics directing this light to the detectors. A controller with processors executes program instructions to receive metrology data from detectors based on collected light. The metrology data includes measurements at multiple tilt angles based on non-zero incidence. The processors determine a bottom critical dimension value at zero-degree incidence by extrapolating measurement data collected at the multiple tilt angles.

A method for determining a process window of a patterning process based on a failure rate. The method includes obtaining a plurality of features printed on a substrate, grouping, based on a metric, the features into a plurality of groups, and generating, based on measurement data associated with a group of features, a base failure rate model for the group of features, wherein the base failure rate model identifies the process window related to the failure rate of the group of features. The method can further include generating, using the base failure rate model, a feature-specific failure rate model for a specific feature, wherein the feature-specific failure rate model identifies a feature-specific process window such that an estimated failure rate of the specific feature is below a specified threshold.

Provided are a method and an apparatus for determining a process window and a computer device. A surface plasmon photolithography model corresponding to a surface plasmon photolithography structure with an air layer is established. A simulation is performed based on the surface plasmon photolithography model to determine a photoresist pattern formed via photolithography and a critical dimension in the photoresist pattern. A thickness of the air layer and/or exposure energy in the surface plasmon photolithography model are adjusted and the simulation is performed based on the surface plasmon photolithography model repeatedly, to obtain multiple correspondences between the exposure energy, the thickness of the air layer, and the critical dimension. Based on the correspondences and a tolerance range allowed for a critical dimension between the photoresist pattern and a pattern of a mask layer corresponding to the photoresist pattern, the process window corresponding to the mask layer is determined.