G05F1/445

VOLTAGE REGULATOR CIRCUIT WITH CURRENT LIMITER STAGE

Examples are disclosed herein that relate to automatically limiting an output current of a voltage regulator circuit responsive to detecting that the voltage regulator is in a current overload mode. In one example, a voltage regulator circuit includes an amplifier stage and a current limiter stage electrically connected to an output of the amplifier stage. The amplifier stage is configured to output a DC voltage based on a reference voltage and feedback from an output voltage. The current limiter stage is configured to operate in a quiescent mode and an overload mode. In the quiescent mode, the current limiter stage is configured to operate as a buffer stage that forms a closed feedback loop to an input of the amplifier stage. In the overload mode, the current limiter stage is configured to act as a current source that clamps an output current to a designated current.

LOW-DROPOUT REGULATION OF OUTPUT VOLTAGE USING FIRST BUFFER AND SECOND BUFFER

A circuit configured to perform low-dropout regulation of an output voltage includes a first buffer, a second buffer, controller circuitry, and switching circuitry. The first buffer includes a first driving element configured to provide a first current into a first output node based on the output voltage. The first bias circuitry is configured to bias the first current. The second buffer includes a second driving element configured to provide a second current into a second output node based on a voltage at the first output node. The second bias circuitry is configured to bias the second current. The controller circuitry is configured to generate a control signal based on a current at the pass device and switching circuitry configured to electrically couple the first output node to the control node of the pass device based on the control signal.

LOW-DROPOUT REGULATION OF OUTPUT VOLTAGE USING FIRST BUFFER AND SECOND BUFFER

A circuit configured to perform low-dropout regulation of an output voltage includes a first buffer, a second buffer, controller circuitry, and switching circuitry. The first buffer includes a first driving element configured to provide a first current into a first output node based on the output voltage. The first bias circuitry is configured to bias the first current. The second buffer includes a second driving element configured to provide a second current into a second output node based on a voltage at the first output node. The second bias circuitry is configured to bias the second current. The controller circuitry is configured to generate a control signal based on a current at the pass device and switching circuitry configured to electrically couple the first output node to the control node of the pass device based on the control signal.

ADAPTABLE LOW DROPOUT (LDO) VOLTAGE REGULATOR AND METHOD THEREFOR

An adaptable LDO regulator includes an error amplifier providing an error voltage according to a difference between a feedback voltage and a reference voltage, first and second pass transistors each having a first current electrode for receiving an input voltage, a control electrode for receiving the error voltage, and a second current electrode, the second current electrode of the second pass transistor providing an output voltage, a voltage divider generating the feedback voltage in response to a voltage on an input thereof, and a mode selection network that in a closed loop mode, couples the second current electrodes of the first and second pass transistors together and to the input of the voltage divider, and in an open loop mode, couples the second current electrode of the first pass transistor to the input of the voltage divider and decouples the second current electrodes of the first and second pass transistors.

ADAPTABLE LOW DROPOUT (LDO) VOLTAGE REGULATOR AND METHOD THEREFOR

An adaptable LDO regulator includes an error amplifier providing an error voltage according to a difference between a feedback voltage and a reference voltage, first and second pass transistors each having a first current electrode for receiving an input voltage, a control electrode for receiving the error voltage, and a second current electrode, the second current electrode of the second pass transistor providing an output voltage, a voltage divider generating the feedback voltage in response to a voltage on an input thereof, and a mode selection network that in a closed loop mode, couples the second current electrodes of the first and second pass transistors together and to the input of the voltage divider, and in an open loop mode, couples the second current electrode of the first pass transistor to the input of the voltage divider and decouples the second current electrodes of the first and second pass transistors.

AMPLIFIER AND VOLTAGE GENERATION CIRCUIT INCLUDING THE SAME
20220019252 · 2022-01-20 · ·

A voltage generation circuit includes an amplifier configured to detect a difference between a reference voltage and a feedback voltage according to a control signal and a bias current, and configured to generate a driving signal. The voltage generation circuit also includes a driver configured to generate an internal voltage by driving an external voltage according to the driving signal. The amount of the bias current may be forcibly adjusted by the control signal.

AMPLIFIER AND VOLTAGE GENERATION CIRCUIT INCLUDING THE SAME
20220019252 · 2022-01-20 · ·

A voltage generation circuit includes an amplifier configured to detect a difference between a reference voltage and a feedback voltage according to a control signal and a bias current, and configured to generate a driving signal. The voltage generation circuit also includes a driver configured to generate an internal voltage by driving an external voltage according to the driving signal. The amount of the bias current may be forcibly adjusted by the control signal.

DECODER SYSTEMS AND METHODS FOR IRRIGATION CONTROL
20230397552 · 2023-12-14 ·

An irrigation system comprises an irrigation controller that receives user input and provides a power signal and command and message data to an encoder. The encoder encodes the command and message data onto the power signal to provide a data encoded power waveform that is sent over a two-wire path. The irrigation system further comprises one or more decoders in communication with the two-wire path to receive the data encoded power waveform and one or more irrigation valves in communication with the one or more decoders. The data encoded power waveform provides power to the decoders and the decoders decode the command and message data from the data encoded power waveform to control the irrigation valves according to the user input.

DECODER SYSTEMS AND METHODS FOR IRRIGATION CONTROL
20230397552 · 2023-12-14 ·

An irrigation system comprises an irrigation controller that receives user input and provides a power signal and command and message data to an encoder. The encoder encodes the command and message data onto the power signal to provide a data encoded power waveform that is sent over a two-wire path. The irrigation system further comprises one or more decoders in communication with the two-wire path to receive the data encoded power waveform and one or more irrigation valves in communication with the one or more decoders. The data encoded power waveform provides power to the decoders and the decoders decode the command and message data from the data encoded power waveform to control the irrigation valves according to the user input.

APPARATUSES AND METHODS INVOLVING SWITCHING BETWEEN DUAL INPUTS OF POWER AMPLICATION CIRCUITRY

An example apparatus includes power amplification circuitry and current-level switch circuitry. The power amplification circuitry has a first input port, a second input port, and field-effect transistor (FET) circuitry, the FET circuitry to operate in a saturation mode while drawing power provided at the first input port from a first power source. The current-level switch circuitry is to sense a change in a current-level used to maintain the FET circuitry in the saturation mode and, in response to the sensed change in the current-level, to cause the power amplification circuitry to draw power provided at the second input port from a second power source while maintaining the saturation mode of the FET circuitry.