Disclosed are a constant current generation circuit for optocoupler isolation amplifier and a current precision adjustment method. The constant current generation circuit includes a start circuit, a current generation circuit and a precision adjustment and output circuit integrated into a same substrate. The start circuit can generate and output a first start current and a second start current. The current generation circuit includes a negative temperature change rate current generation circuit connected to a first start current output and a positive temperature change rate current generation circuit connected to a second start current output. The precision adjustment and output circuit outputs constant current meeting application requirements of optocoupler isolation amplifier by adjusting proportional precision of two currents output from a current generation circuit. The disclosure forms a constant current output circuit which is independent of temperature changes, power supply voltage changes and changes in technological parameters of current sheets.

The invention discloses a method and a system for correction of the junction temperatures of an IGBT module in a photovoltaic inverter. The method includes: constructing an electrothermal coupling model of an IGBT model based on a photovoltaic inverter topology, a light radiation intensity, and an ambient temperature; selecting an IGBT collector-emitter on-state voltage drop as an aging parameter and designing an on-state voltage drop sampling circuit to ensure measurement accuracy; constructing an aging database for IGBT modules in different aging stages based on large current and small current injection methods; comparing a junction temperature value output by the electrothermal coupling model with the calibrated junction temperature value and calibrating an aging process coefficient of an electrothermal coupling model correction formula; comparing an IGBT aging monitoring value with the aging threshold to determine the aging process and selecting a corresponding aging process coefficient to ensure accuracy of junction temperature data.

The invention discloses a method and a system for correction of the junction temperatures of an IGBT module in a photovoltaic inverter. The method includes: constructing an electrothermal coupling model of an IGBT model based on a photovoltaic inverter topology, a light radiation intensity, and an ambient temperature; selecting an IGBT collector-emitter on-state voltage drop as an aging parameter and designing an on-state voltage drop sampling circuit to ensure measurement accuracy; constructing an aging database for IGBT modules in different aging stages based on large current and small current injection methods; comparing a junction temperature value output by the electrothermal coupling model with the calibrated junction temperature value and calibrating an aging process coefficient of an electrothermal coupling model correction formula; comparing an IGBT aging monitoring value with the aging threshold to determine the aging process and selecting a corresponding aging process coefficient to ensure accuracy of junction temperature data.

A voltage reference circuit that can operate in a large supply voltage range with high PSRR, that dissipates low-power for a given output noise, and that has a low temperature-coefficient (TC) across a wide-temperature range. The voltage reference circuit does not require any calibration for low TC and high PSRR, occupies a relatively small circuit area, may be used without additional supply filtering in noisy or high-ripple supply environments, and is more robust against device mismatch effects particularly compared to designs based on sub-threshold operations. The voltage reference circuit is a special form of constant transconductance circuit that uses current mirror ratios that are chosen to achieve high PSSR and low noise properties. The device saturation voltage may be chosen so that flat temperature characteristics may be achieved.

A voltage reference circuit that can operate in a large supply voltage range with high PSRR, that dissipates low-power for a given output noise, and that has a low temperature-coefficient (TC) across a wide-temperature range. The voltage reference circuit does not require any calibration for low TC and high PSRR, occupies a relatively small circuit area, may be used without additional supply filtering in noisy or high-ripple supply environments, and is more robust against device mismatch effects particularly compared to designs based on sub-threshold operations. The voltage reference circuit is a special form of constant transconductance circuit that uses current mirror ratios that are chosen to achieve high PSSR and low noise properties. The device saturation voltage may be chosen so that flat temperature characteristics may be achieved.

A low-power CMOS reference voltage generating with enhanced power supply rejection ratio (PSRR) and fast start-up time is disclosed. The reference voltage generating is generated by the stacked diode-connected MOS transistors (SDMT) architecture to reduce the dependence on process, voltage and temperature. The self-biased and capacitor coupled architecture can shorten the start-up time without increasing power consumption and improve the bandwidth of the power supply rejection ratio. This design is implemented using a CMOS process, which can achieve stabilization time of 0.2 ms. Under the same power consumption, this design is 274 times better than a design without a start-up time enhancement. The power supply rejection ratio measured at 100 Hz is −73.5 dB. In the temperature range of −40 to 130° C., the average temperature coefficient is 62 ppm/° C.

A low-power CMOS reference voltage generating with enhanced power supply rejection ratio (PSRR) and fast start-up time is disclosed. The reference voltage generating is generated by the stacked diode-connected MOS transistors (SDMT) architecture to reduce the dependence on process, voltage and temperature. The self-biased and capacitor coupled architecture can shorten the start-up time without increasing power consumption and improve the bandwidth of the power supply rejection ratio. This design is implemented using a CMOS process, which can achieve stabilization time of 0.2 ms. Under the same power consumption, this design is 274 times better than a design without a start-up time enhancement. The power supply rejection ratio measured at 100 Hz is −73.5 dB. In the temperature range of −40 to 130° C., the average temperature coefficient is 62 ppm/° C.

A circuit for controlling electrical power is described herein. In accordance with one embodiment, the circuit comprises: a circuit node operably connected to a pass element configured to be switched on and off in accordance with a drive signal applied at the circuit node; a communication interface configured to receive data from an external controller operably connected to the communication interface; and a control circuit configured to generate, in a first mode of operation, the drive signal dependent on parameters of a first parameter set and based on data received via the communication interface, and to generate, in a second mode of operation, the drive signal dependent on parameters of a second parameter set while discarding data received via the communication interface.

A circuit for controlling electrical power is described herein. In accordance with one embodiment, the circuit comprises: a circuit node operably connected to a pass element configured to be switched on and off in accordance with a drive signal applied at the circuit node; a communication interface configured to receive data from an external controller operably connected to the communication interface; and a control circuit configured to generate, in a first mode of operation, the drive signal dependent on parameters of a first parameter set and based on data received via the communication interface, and to generate, in a second mode of operation, the drive signal dependent on parameters of a second parameter set while discarding data received via the communication interface.

A multi-phase control circuit and a temperature balance control method thereof The temperature balance control method of the multi-phase control circuit includes the steps of: acquiring a first temperature signal reflecting a representative temperature among a plurality of power stages, then acquiring a plurality of second temperature signals reflecting a respective temperature of each of the plurality of power stages; and adjusting a pulse width and/or frequency of a pulse width modulation signal of at least one of the plurality of power stages according to a comparison result between the first temperature signal and the second temperature signal so as to balance the temperatures of the plurality of power stages.