A circuit includes: a cascode current source comprising: a current mirror transistor; and a cascode transistor; and a bias circuit coupled to the cascode current source, the bias circuit comprising: a current source; a first transistor coupled in series to the current source to form a first current path through the current source and the first transistor; a second transistor coupled in series to the current source; and a third transistor coupled in series to the second transistor and the current source to form a second current path through the current source and the second and third transistors, wherein the third transistor has a channel size greater than a channel size of the second transistor by a multiple determined according to a design factor of the bias circuit.

A switch bias control circuit includes a level shifter and voltage regulator circuitry configured to receive a voltage reference signal, provide a first voltage output at a first node and provide a second voltage output at a second node, the first node and the second node being at least partially isolated from one another. coupling circuitry couples the first node to the level shifter and couples the second node to a negative voltage generator.

One or more embodiments relate to a multi-bias mode current conveyor. Such a current conveyor may include an input terminal, a reference terminal, an output terminal, a first and second cascoded current mirrors, and a biasing circuit. The first cascoded current mirror and a second cascoded current mirror may be arranged as a current conveyor that is configured to provide an output current that a mirror of an input current. The biasing circuit may be configured to provide a bias voltage selectively exhibiting a first voltage level or a second voltage level. The bias voltage may be provided at least partially responsive to a state of the input current. The biasing circuit may be arranged to apply the bias voltage to at least one of the first cascoded current mirror or the second cascoded current mirror.

Techniques for providing temperature trim codes to multiple reference circuits of an integrated circuit are provided. In an example, a string of primary latch circuits can provide a set of pre-defined temperature trim codes to a multiplexer in response to a token of a series of tokens. The multiplexer can provide two trim of the trim codes to an interpolator based on a temperature reading of the integrated circuit. The interpolator can provide an interpolated trim code and the trim code can be distributed to a reference circuit based on the token.

Techniques for providing temperature trim codes to multiple reference circuits of an integrated circuit are provided. In an example, a string of primary latch circuits can provide a set of pre-defined temperature trim codes to a multiplexer in response to a token of a series of tokens. The multiplexer can provide two trim of the trim codes to an interpolator based on a temperature reading of the integrated circuit. The interpolator can provide an interpolated trim code and the trim code can be distributed to a reference circuit based on the token.

In an embodiment, a circuit provided by the present invention includes a transistor connected to allow current to flow from a voltage supply to an output port. The circuit further includes a resistance ladder digital-to-analog converter (R.sub.DAC) configured to receive a digital input that indicates a voltage scaling factor. The R.sub.DAC is further configured to receive an input voltage (V.sub.B) at a voltage input port and produce an output voltage (V.sub.A). The circuit further includes an amplifier having an output port connected to a gate of the first transistor, an inverting input port receiving the output voltage (V.sub.A), and a non-inverting input connected to the output port of the first transistor.

An electronic device includes: an integrated circuit including a first power source terminal to which a first voltage is supplied from a DC power source, a second power source terminal to which a second voltage is supplied from the DC power source, a third power source terminal coupled to the first power source terminal through an internal resistance, and a fourth power source terminal coupled to the second power source terminal; and a power source circuit including a first power source line that supplies the first voltage to the first power source terminal from the DC power source, a second power source line that supplies the second voltage to the second power source terminal from the DC power source, and a bypass capacitor coupled between the third power source terminal and the fourth power source terminal.

An electronic device includes: an integrated circuit including a first power source terminal to which a first voltage is supplied from a DC power source, a second power source terminal to which a second voltage is supplied from the DC power source, a third power source terminal coupled to the first power source terminal through an internal resistance, and a fourth power source terminal coupled to the second power source terminal; and a power source circuit including a first power source line that supplies the first voltage to the first power source terminal from the DC power source, a second power source line that supplies the second voltage to the second power source terminal from the DC power source, and a bypass capacitor coupled between the third power source terminal and the fourth power source terminal.

Methods and circuits for adjusting the output parameter of a device wherein the output parameter is temperature dependent are disclosed herein. An example of a method includes: adjusting the output parameter to a target level at a first temperature; adjusting a linear temperature-dependent variable related to the output parameter to zero at the first temperature; adjusting a nonlinear temperature-dependent variable related to the output parameter to zero at the first temperature; adjusting the output parameter to the target level at a second temperature using the linear-dependent variable; adjusting the nonlinear temperature-dependent variable to zero at the second temperature; and adjusting the output parameter to the target level at a third temperature by adjusting the nonlinear variable.

Methods and circuits for adjusting the output parameter of a device wherein the output parameter is temperature dependent are disclosed herein. An example of a method includes: adjusting the output parameter to a target level at a first temperature; adjusting a linear temperature-dependent variable related to the output parameter to zero at the first temperature; adjusting a nonlinear temperature-dependent variable related to the output parameter to zero at the first temperature; adjusting the output parameter to the target level at a second temperature using the linear-dependent variable; adjusting the nonlinear temperature-dependent variable to zero at the second temperature; and adjusting the output parameter to the target level at a third temperature by adjusting the nonlinear variable.