A container scheduling method and apparatus, and a computer-readable storage medium, which relate to the technical field of computers. The method includes: according to a resource usage amount of a container set copy which has run, determining a predicted resource usage amount of a container set copy to be scheduled, wherein the type of container set copy which has run is the same as the type of container set copy to be scheduled; according to the predicted resource usage amount and a resource supply amount supported by each candidate node, determining a candidate node matching the container set copy which has run; and scheduling the container set copy which has run to the matched candidate node for running.

A container scheduling method and apparatus, and a computer-readable storage medium, which relate to the technical field of computers. The method includes: according to a resource usage amount of a container set copy which has run, determining a predicted resource usage amount of a container set copy to be scheduled, wherein the type of container set copy which has run is the same as the type of container set copy to be scheduled; according to the predicted resource usage amount and a resource supply amount supported by each candidate node, determining a candidate node matching the container set copy which has run; and scheduling the container set copy which has run to the matched candidate node for running.

An operational circuit of a virtual currency data processing device includes: at least two operational chip groups (31) configured to operate within respective operating voltage threshold ranges of the operational chip groups (31) to receive a communication signal which includes an issued task, perform calculations according to the issued task, and transmit a communication signal which includes a calculation result; a control module (32) configured to operate within an operating voltage threshold range of the control module (32) to transmit the communication signal which includes the issued task and receive the communication signal which includes the calculation result; at least two signal forwarding and electrical isolation modules, each of which is communicatively connected to the control module and a respective operational chip group and is configured to forward communication signals between the control module and the respective operational chip group, and isolate an operating voltage threshold of the operational chip groups from an operating voltage threshold of the control module to make the operational chip groups and the control module capable of identifying communication signals sent by each other.

According to various embodiments of the present disclosure, an electronic device includes: a housing; a touch circuit including a plurality of TX electrodes, and a plurality of RX electrodes arranged to cross over the plurality of TX electrode; a flexible display which includes the touch circuit, and which can be withdrawn from the inner space of the housing; a touch controller; and a processor operatively connected to the touch circuit, the flexible display and the touch controller, wherein the touch controller applies a driving signal by using the plurality of TX electrodes of the touch circuit, acquires the driving signal by using the plurality of RX electrodes, confirms a capacitance value on the basis of the acquired driving signal, and confirms information about a folded area of the flexible display on the basis of the capacitance value, and the processor can set an activation area for an unfolded area of the flexible display on the basis of the folded area of the flexible display. Various embodiments, in addition to various embodiments disclosed in the present document, are also possible.

A system for providing system level sleep state power savings includes a plurality of memory channels and corresponding plurality of memories coupled to respective memory channels. The system includes one or more processors operative to receive information indicating that a system level sleep state is to be entered and in response to receiving the system level sleep indication, moves data stored in at least a first of the plurality of memories to at least a second of the plurality of memories. In some implementations, in response to moving the data to the second memory, the processor causes power management logic to shut off power to: at least the first memory, to a corresponding first physical layer device operatively coupled to the first memory and to a first memory controller operatively coupled to the first memory and place the second memory in a self-refresh mode of operation.

A data transmission method is provided, the method is applied to a wearable apparatus configured with a first operation system and a second operation system, and a power consumption of the first operation system is lower than a power consumption of the second operation system; the method; the method includes: obtaining a type of data to be transmitted; detecting current screen state information of the wearable apparatus; and determining target data according to the current screen state information of the wearable apparatus and the type of data to be transmitted, and transmitting the target data from the first operation system of the wearable apparatus to the second operation system of the wearable apparatus.

A circuit comprises a power controller, a real-time clock (RTC) sub-system, and a processing sub-system. The RTC sub-system includes an alarm register storing a predetermined time for a task, and provides an early warning countdown and a scheduled event signal. The processing sub-system includes a processor, a preemptive wakeup circuit, and a component coupled to the processor and configured to execute the task with the processor. The preemptive wakeup circuit comprises a selector logic circuit, a comparator, and a wakeup initiation circuit. The selector logic circuit receives latency values indicative of wakeup times for a clock generator and the component, and outputs a longest wakeup time to the comparator, which indicates when the early warning countdown and the longest wakeup time are equal. The wakeup initiation circuit generates a clock request and disables the sleep mode indicator. The power controller provides a clock signal and wakes the component.

A processing unit is configured differently based on an identified workload, and each configuration of the processing unit is exposed to software (e.g., to a device driver) as a different virtual processing unit. Using these techniques, a processing system is able to provide different configurations of the processing unit to support different types of workloads, thereby conserving system resources. Further, by exposing the different configurations as different virtual processing units, the processing system is able to use existing device drivers or other system infrastructure to implement the different processing unit configurations.

Techniques and mechanisms for providing a thread scheduling hint to an operating system of a processor which comprises first cores and second cores. In an embodiment, the first cores are of a first type which corresponds to a first range of sizes, and the second cores are of a second type which corresponds to a second range of sizes smaller than the first range of sizes. A power control unit (PCU) of the processor is to detect that an inefficiency, of a first operational mode of the processor, would exist while an indication of an amount of power, to be available to the processor, is below a threshold. Based on the detecting, the PCU hints to an executing software process that a given core is to be included in, or omitted from, a pool of cores available for thread scheduling. The hint indicates the given core based on a relative prioritization of the first core type and the second core type.

Techniques and mechanisms for providing a thread scheduling hint to an operating system of a processor which comprises first cores and second cores. In an embodiment, the first cores are of a first type which corresponds to a first range of sizes, and the second cores are of a second type which corresponds to a second range of sizes smaller than the first range of sizes. A power control unit (PCU) of the processor is to detect that an inefficiency, of a first operational mode of the processor, would exist while an indication of an amount of power, to be available to the processor, is below a threshold. Based on the detecting, the PCU hints to an executing software process that a given core is to be included in, or omitted from, a pool of cores available for thread scheduling. The hint indicates the given core based on a relative prioritization of the first core type and the second core type.