Disclosed are a method and apparatus for controlling a hardware module, electronic device and storage medium. In an embodiment of the present disclosure, the method may include: timing a waiting state of the hardware module to obtain a current waiting duration of the hardware module when it enters a first waiting state; generating an interrupt signal based on the current waiting duration; determining program information corresponding to the current waiting duration under triggering from the interrupt signal; executing an action corresponding to the program information for the hardware module, and controlling it to enter a second waiting state. In the present disclosure, the hardware module is controlled to execute actions corresponding to different programs based on different waiting durations through an interrupt mechanism, thus controlling the hardware module to switch between waiting states with different power consumption, and achieving a good balance between energy saving and performance.

Disclosed herein are embodiments of systems and methods for stable and elevated idle-mode temperature for assembled semiconductor devices. In an embodiment, a processor includes a communication interface configured to receive, from a first hardware component, instructions assigned to the processor for execution. The processor also includes temperature-measurement circuitry configured to monitor an on-chip temperature of the processor. The processor also includes control logic configured to: determine whether the processor is active or idle; determine whether the on-chip temperature of the processor exceeds a first threshold; based on determining that the processor is idle and that the on-chip temperature of the processor exceeds the first threshold, disable one or more idle-mode power-saving features of the processor; and selectively adjust one or more operating parameters of the processor to keep the on-chip temperature of the processor between the first threshold and a second (higher) threshold.

Methods and apparatuses for improve clocking scheme to reduce power consumption are presented. The apparatus includes a host configured to communicate with a memory via a link. The host is further configured to receive a first clock from the memory; to receive, based on the first clock, data from the memory, in a first mode of a read operation; to generate a second clock, the second clock being generated independent of the first clock; and to receive, based on the second clock, data from the memory, in a second mode of the read operation.

A dynamic power reduction method and apparatus for use in an ultrasound system are described. In one embodiment, the ultrasound system comprises: a transducer assembly and imaging subsystem having a transmit data path having a transmitter to transmit acoustic signals and a receive data path having including signal acquisition circuitry with a receiver to receive acoustic signals representing echoes; a plurality of real-time signals indicative of status of imaging operations being performed by the transmit and receive paths; a clock generator to generate one or more clocks for use by the transmit and receive data paths; clock gating circuitry coupled to the clock generator and the transmit and receive paths and having circuits to gate clocks to at least one of the transmit and receive paths; and a clock gating controller coupled to the clock gating circuitry to control the circuits to gate or pass clock signals to at least one of the transmit and receive paths automatically in response to receipt of one or more signals from the plurality of real-time signals.

A dynamic power reduction method and apparatus for use in an ultrasound system are described. In one embodiment, the ultrasound system comprises: a transducer assembly and imaging subsystem having a transmit data path having a transmitter to transmit acoustic signals and a receive data path having including signal acquisition circuitry with a receiver to receive acoustic signals representing echoes; a plurality of real-time signals indicative of status of imaging operations being performed by the transmit and receive paths; a clock generator to generate one or more clocks for use by the transmit and receive data paths; clock gating circuitry coupled to the clock generator and the transmit and receive paths and having circuits to gate clocks to at least one of the transmit and receive paths; and a clock gating controller coupled to the clock gating circuitry to control the circuits to gate or pass clock signals to at least one of the transmit and receive paths automatically in response to receipt of one or more signals from the plurality of real-time signals.

A disclosed technique includes triggering entry into a clock bypass mode, in which a bypass clock generator provides clock signals to functional elements and a primary clock generator does not provide clock signals to functional elements; and triggering exit from the clock bypass mode, in which the bypass clock generator does not provide clock signals to the functional elements and the primary clock generator does provide clock signals to the functional elements.

A disclosed technique includes triggering entry into a clock bypass mode, in which a bypass clock generator provides clock signals to functional elements and a primary clock generator does not provide clock signals to functional elements; and triggering exit from the clock bypass mode, in which the bypass clock generator does not provide clock signals to the functional elements and the primary clock generator does provide clock signals to the functional elements.

A data processor includes a plurality of requestors, a plurality of responders, and a data fabric. The data fabric is for routing requests between the plurality of requestors and the plurality of responders and has a plurality of non-operational power states including a normal C-state and a light-weight C-state. The light-weight C-state has lower entry and exit latencies than the normal C-state. The data fabric monitors traffic through the data fabric and places the data fabric in the light-weight C-state in response to detecting an idle traffic state.

A method, a device, and an integrated circuit utilizes a temperature restricted mode. The method includes determining a temperature of the device. When the temperature is below a first threshold, the method includes enabling a first mode comprising select network operations. When the temperature is above a brick threshold, the method includes enabling a second mode comprising disabling the select network operations. When the temperature is above the first threshold and below the brick threshold, the method includes enabling a third mode comprising modifying at least one of the select network operations.

A data fabric routes requests between the plurality of requestors and the plurality of responders. The data fabric includes a crossbar router, a coherent slave controller coupled to the crossbar router, and a probe filter coupled to the coherent slave controller and tracking the state of cached lines of memory. Power state control circuitry operates, responsive to detecting any of a plurality of designated conditions, to cause the probe filter to enter a retention low power state in which a clock signal to the probe filter is gated while power is maintained to the probe filter. Entering the retention low power state is performed when all in-process probe filter lookups are complete.