Processor-based systems employing local dynamic power management based on controlling performance and operating power consumption, and related methods. The processor-based system is configured to locally manage its power consumption by dynamically adjusting operating frequency and/or operating voltage of power supplied to the processor-based system. The processor-based system includes a power control circuit that is aware of the overall power budget for the processor-based system. The control processor in the processor-based system can dynamically increase the voltage level of the power supplied to the processor-based system and/or the operating frequency if the consumed power is lower than the power budget. The power control circuit can also dynamically decrease the operating frequency and/or the voltage level of the power supplied to the processor-based system if the consumed power is higher than the power budget.

According to at least one example embodiment, a method and corresponding apparatus for controlling power in a multi-core processor chip include: accumulating, at a controller within the multi-core processor chip, one or more power estimates associated with multiple core processors within the multi-core processor chip. A global power threshold is determined based on a cumulative power estimate, the cumulative power estimate being determined based at least in part on the one or more power estimates accumulated. The controller causes power consumption at each of the core processors to be controlled based on the determined global power threshold. The controller may directly control power consumption at the core processors or may command the core processors to do so.

According to at least one example embodiment, a method and corresponding apparatus for controlling power in a multi-core processor chip include: accumulating, at a controller within the multi-core processor chip, one or more power estimates associated with multiple core processors within the multi-core processor chip. A global power threshold is determined based on a cumulative power estimate, the cumulative power estimate being determined based at least in part on the one or more power estimates accumulated. The controller causes power consumption at each of the core processors to be controlled based on the determined global power threshold. The controller may directly control power consumption at the core processors or may command the core processors to do so.

Disclosed is an electronic device which includes a main processor, and a systolic array processor, and the systolic array processor includes processing elements, a kernel data memory that provides a kernel data set to the processing elements, a data memory that provides an input data set to the processing elements, and a controller that provides commands to the processing elements. The main processor translates source codes associated with the systolic array processor into commands of the systolic array processor, calculates a switching activity value based on the commands, and stores the translated commands and the switching activity value to a machine learning module, which is based on the systolic array processor.

A method of an electronic device are provided in which current consumption for one or more components of the electronic device is compared with a predetermined current. A first surface temperature of the electronic device is determined based on the comparison and power consumption of the one or more components. A location is detected where heat corresponding to the first surface temperature is generated. A second surface temperature of the electronic device is obtained based on power consumption of a component disposed in the electronic device corresponding to the location where the heat is generated. A target temperature is set based on the obtained second surface temperature. The component is controlled to reduce the power consumption of the component based on the target temperature.

A method of an electronic device are provided in which current consumption for one or more components of the electronic device is compared with a predetermined current. A first surface temperature of the electronic device is determined based on the comparison and power consumption of the one or more components. A location is detected where heat corresponding to the first surface temperature is generated. A second surface temperature of the electronic device is obtained based on power consumption of a component disposed in the electronic device corresponding to the location where the heat is generated. A target temperature is set based on the obtained second surface temperature. The component is controlled to reduce the power consumption of the component based on the target temperature.

A single communication fabric for a data processing apparatus is provided. The fabric has an interconnection network to provide a topology of data communication channels between a plurality of data-handling functional units. The interconnection network has a first interconnection domain to provide data communication between a first subset of the data-handling functional units and a second interconnection domain to provide data communication between a second subset of the data-handling functional units. The power management circuitry is arranged to control a first performance level for the first interconnection domain independently from control of a second performance level for the second interconnection domain. Machine readable instructions and a method are provided to concurrently set performance levels of two different fabric domains to respective different operating frequencies.

A single communication fabric for a data processing apparatus is provided. The fabric has an interconnection network to provide a topology of data communication channels between a plurality of data-handling functional units. The interconnection network has a first interconnection domain to provide data communication between a first subset of the data-handling functional units and a second interconnection domain to provide data communication between a second subset of the data-handling functional units. The power management circuitry is arranged to control a first performance level for the first interconnection domain independently from control of a second performance level for the second interconnection domain. Machine readable instructions and a method are provided to concurrently set performance levels of two different fabric domains to respective different operating frequencies.

A control method of a power supply path includes detecting a plug-in state of a first connector through a configuration channel pin of the first connector; acquiring a plurality of rated voltages of a first power adaptor externally connected to the first connector and a rated current corresponding to each of the rated voltages; detecting a plug-in state of a second connector through a direct-current (DC) input pin of the second connector; acquiring a power quota of a second power adaptor externally connected to the second connector; selecting, from the plurality of rated voltages, the largest one that is not greater than an operating voltage, as a selected rated voltage; calculating a power quota of the selected rated voltage; and controlling a switching circuit to couple a power circuit to a power pin of one of the first and second connectors according to the two power quotas.

In an embodiment a method includes generating a low-frequency clock signal having a first frequency, in a standby mode and in a run mode of the CPU, generating a high-frequency clock signal having a second frequency higher than the first frequency, in the run mode, updating a value of the reference time base at each period of the low-frequency clock signal in the standby mode, and accessing the counter register with the high-frequency clock signal in the run mode.