An application processor includes a main central processing device that operates based on an external main clock signal received from at least one external clock source when the application processor is in an active mode, at least one internal clock source that generates an internal clock signal, and a sensor sub-system that processes sensing-data received from at least one sensor module on a predetermined cycle when the application processor is in the active mode or a sleep mode, and that operates based on the internal clock signal or an external sub clock signal received from the external clock source depending on an operating speed required for processing the sensing-data.

An application processor includes a main central processing device that operates based on an external main clock signal received from at least one external clock source when the application processor is in an active mode, at least one internal clock source that generates an internal clock signal, and a sensor sub-system that processes sensing-data received from at least one sensor module on a predetermined cycle when the application processor is in the active mode or a sleep mode, and that operates based on the internal clock signal or an external sub clock signal received from the external clock source depending on an operating speed required for processing the sensing-data.

The present invention provides a power control circuit and control method. The power control circuit includes: a control module configured to control, according to an activation command, a memory bank of a plurality of memory banks to perform an operation; a power management module configured to wake up a local power supply for the memory bank according to a clock enable signal; and a power control module communicatively coupled with the power management module and configured to: send the clock enable signal to the power management module of the memory bank corresponding to the activation command in a power-saving mode; and send the clock enable signal to power management modules of the plurality of memory banks in a non-power-saving mode, where the power-saving mode indicates that a system clock is in a low-frequency state.

The present invention provides a power control circuit and control method. The power control circuit includes: a control module configured to control, according to an activation command, a memory bank of a plurality of memory banks to perform an operation; a power management module configured to wake up a local power supply for the memory bank according to a clock enable signal; and a power control module communicatively coupled with the power management module and configured to: send the clock enable signal to the power management module of the memory bank corresponding to the activation command in a power-saving mode; and send the clock enable signal to power management modules of the plurality of memory banks in a non-power-saving mode, where the power-saving mode indicates that a system clock is in a low-frequency state.

A point-of-sale (POS) device includes a processor, a battery, a transaction object reader, a printer with a printer controller, and optionally a temperature sensor. The processor determines a present power discharge capability rate of the battery, optionally based on a temperature measured by the temperature sensor. The processor also calculates a first estimated power draw rate based on a first setting value for at least one of the components of the POS device, such as the printer. If the first estimated power draw rate is dangerously close to the present power discharge capability rate of the battery, a second estimated power draw rate is calculated based on a second setting value for the one or more components. If the second estimated power draw rate is no longer dangerously close to the present power discharge capability rate of the battery, the components are set to the second settings value.

A point-of-sale (POS) device includes a processor, a battery, a transaction object reader, a printer with a printer controller, and optionally a temperature sensor. The processor determines a present power discharge capability rate of the battery, optionally based on a temperature measured by the temperature sensor. The processor also calculates a first estimated power draw rate based on a first setting value for at least one of the components of the POS device, such as the printer. If the first estimated power draw rate is dangerously close to the present power discharge capability rate of the battery, a second estimated power draw rate is calculated based on a second setting value for the one or more components. If the second estimated power draw rate is no longer dangerously close to the present power discharge capability rate of the battery, the components are set to the second settings value.

A method includes receiving a power supply unit (“PSU”) replacement signal for a power supply chassis that includes plurality of supply enclosures. Each power supply enclosure includes a plurality of power supply units (“PSUs”). Each of the PSUs in the power supply enclosures is connected to a power bus powering computing equipment. PSU redundancy policy has at least one PSU being redundant. In response to the PSU replacement signal, the method calculates a power cap limit equal to a capacity of the plurality of supply enclosures that are not being removed. Power consumption of the computing equipment is limited to the power cap limit. In response to detecting a replacement power supply enclosure, the method recalculates the power cap limit based on all of the PSUs according to the PSU redundancy policy. Power consumption of the computing equipment is limited to the recalculated power cap limit.

A method includes receiving a power supply unit (“PSU”) replacement signal for a power supply chassis that includes plurality of supply enclosures. Each power supply enclosure includes a plurality of power supply units (“PSUs”). Each of the PSUs in the power supply enclosures is connected to a power bus powering computing equipment. PSU redundancy policy has at least one PSU being redundant. In response to the PSU replacement signal, the method calculates a power cap limit equal to a capacity of the plurality of supply enclosures that are not being removed. Power consumption of the computing equipment is limited to the power cap limit. In response to detecting a replacement power supply enclosure, the method recalculates the power cap limit based on all of the PSUs according to the PSU redundancy policy. Power consumption of the computing equipment is limited to the recalculated power cap limit.

A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.

A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.