A method by a computing system of a device includes receiving a request to render a frame comprising one or more virtual content and determining, for the one or more virtual content, an associated characteristic. The method further includes determining whether to reduce a rendering workload associated with rendering the frame to satisfy one or more power or thermal constraints associated with the device. In response to a determination to reduce the rendering workload, the method further includes generating a set of rending parameters for rendering the frame in order to reduce the rendering workload. At least one rendering parameter in the set of rendering parameters is determined based on the characteristic associated with the one or more virtual content. The method thus includes rendering the frame in accordance with the set of rending parameters so as to satisfy the one or more power or thermal constraints.

A branch predictor of a processor includes one or more prediction structures, including a predicted branch address and predicted branch direction, that identify predicted branches. To reduce power consumption, the branch predictor selects one or more of the prediction structures that are not expected to provide useful branch prediction information and filters the selected structures such that the filtered structures are not used for branch prediction. The branch predictor thereby reduces the amount of power used for branch prediction without substantially reducing the accuracy of the predicted branches.

In various examples, permanent faults in hardware component(s) and/or connections to the hardware component(s) of a computing platform may be predicted before they occur using in-system testing. As a result of this prediction, one or more remedial actions may be determined to enhance the safety of the computing platform (e.g., an autonomous vehicle). A degradation rate of a performance characteristic associated with the hardware component may be determined, detected, and/or computed by monitoring values of performance characteristics over time using fault testing.

The present disclosure relates to a computing system. The computing system comprises a data input configured to receive an input data signal, a computation unit having an input coupled with the data input, the computation unit being operative to apply a weight to a signal received at its input to generate a weighted output signal, and a controller. The controller is configured to monitor a parameter of the input signal and/or a parameter of the output signal and to issue a control signal to the computation unit to control a level of accuracy of the weighted output signal based at least in part on the monitored parameter.

The present invention provides a circuitry applied to multiple power domains. An amplifier of the circuitry includes an output stage and a switching circuit. The output stage includes a first transistor and a second transistor, wherein the first transistor is coupled between a supply voltage and an output terminal, the second transistor is coupled between the output terminal and a ground voltage. The switching circuit is configured to choose a body of the first transistor from the supply voltage or a reference voltage.

A storage device includes non-volatile memory, a storage controller including a first controller processor connected to the non-volatile memory, and a second controller processor connected to the non-volatile memory, and shared memory to store a mapping table. The shared memory may be connected to the first controller processor and the second controller processor to share mapping table information between the first controller processor and the second controller processor. The storage controller may set a power mode of the first controller processor and the second controller processor based on an input/output intensity.

System on chip including plurality of processors including first and second processors; plurality of intellectual properties (IPs) including first and second IPs; memory interface; internal clock circuit to receive reference clock signal, generate first internal clock signal, and provide first internal clock signal to first IP; memory interface clock circuit to receive reference clock signal, generate memory interface clock signal, and provide memory interface clock signal to memory interface; and power management unit (PMU), wherein first internal clock signal drives first IP, memory interface clock signal drives memory interface, PMU generates first control signal based on operational states of plurality of processors, and provides first control signal to internal clock circuit, PMU generates second control signal based on operational states of plurality of processors, and provides second control signal to memory interface clock circuit, internal clock circuit sets clock rate of first internal clock signal based on first control signal, and memory interface clock circuit sets clock rate of memory interface clock signal based on second control signal.

A thermal management scheme, for a multichip module, that is aware of various dies in a stack (horizontal and/or vertical) and heat generated from them, local hot spots in a victim die, and hot spots in aggressor die(s). Each victim die receives telemetry information from thermal sensors located in aggressor dies as well as local thermal sensors in the victim die. The telemetry information is used to enable a virtual sensing scheme where temperature for a target die (e.g., a victim die) and/or its intellectual property (IP) domain is estimated or calculated. The estimated or calculated temperature is then used for performance management of the victim and/or aggressor dies in the stack.

A system for remotely measuring the characteristics of water passing through a plumbing control device (PCD) includes a sensor within the interior of the PCD. The sensor is configured to measure characteristics of the water to obtain measured data. The sensor is also linked to a microcontroller of the PCD. An antenna board is linked, and configured to transmit power, to both the microcontroller and the sensor. A mobile device is configured to locate the antenna board. The mobile device transmits power to the antenna board which, in turn, transmits power to the microcontroller and the sensor. When power is not being transmitted from the antenna board, the microcontroller and the sensor are powered off.

Various embodiments may include methods and systems for power management of multiple chiplets within a system-on-a-chip (SoC). Various systems may include a power management integrated circuit (PMIC) configured to supply power to a first chiplet and a second chiplet across a shared power rail. The first chiplet may be configured to obtain first sensory information throughout the first chiplet. The second chiplet may be configured to obtain second sensory information throughout the second chiplet, and may be configured to transmit a voltage change message to the first chiplet based on the second sensory information. The first chiplet may be configured to transmit a power rail adjustment message to the PMIC based on the first sensory information and the voltage change message. The PMIC may be configured to adjust the voltage of at least one of the first chiplet and the second chiplet.