Patent classifications
G06F1/3243
CAPACITIVE INTELLIGENT WORKSTATION DETECTION SYSTEM
A capacitive intelligent workstation detection system, comprising a capacitance detection sensor (1), a capacitive sensing module (201), a microprocessor module (202), a remote management platform (3) and a mobile APP, the capacitance detection sensor (1) detecting a capacitance change when a human body approaches, and after being processed by the capacitive sensing module (201), the capacitance change being sent to the microprocessor module (202) to form workstation state data, the workstation state data being sent to the remote management platform (3), and the remote management platform (3) processing the workstation state data, so as to obtain user habit data. A user uses the mobile APP to obtain relevant data by means of the remote management platform (3), and sends debugging and control information to a workstation detection device (2). The system uses the capacitive sensing module (201), has a small volume, a good concealment, a beautiful appearance and a flexible design, does not require complex optical and microwave devices and has no mechanical device, is less vulnerable to aging and abrasion, and has a long service life and good consistency. The remote management platform (3) serves as a data management and control center, and the mobile APP provides man-machine bidirectional interaction, so as to implement office electric appliance linkage energy-saving management and personnel management.
Power Consumption Control Method and Device
A power consumption control method includes obtaining, by a wireless access device, characteristic data of one or more first components, where the characteristic data indicates a running status of the wireless access device; determining, by the wireless access device, target power consumption statuses of a plurality of second components based on the characteristic data; and adjusting, by the wireless access device, power consumption statuses of the second components based on the target power consumption statuses.
HEAT PIPE DRYOUT PREVENTION
Methods, apparatus, systems, and articles of manufacture are disclosed that prevent heat pipe dryout. An example apparatus includes processor circuitry to at least one of instantiate or execute machine readable instructions to: determine if a temperature of a heat pipe of an electronic device is below a first threshold temperature; cause a program to switch from a first operating mode to a second operating mode when the temperature is below the first threshold temperature, the second operating mode to use more processor circuitry bandwidth than the first operating mode; determine at least one of (1) an occurrence of an increase in a power level of the electronic device or (2) the temperature of the heat pipe satisfies a second threshold temperature; and cause the program to switch from the second operating mode to the first operating mode based on at least one of (1) the occurrence of the increase in the power level or (2) the temperature of the heat pipe satisfying the second threshold temperature.
METHOD AND APPARATUS FOR POWER SAVING IN SEMICONDUCTOR DEVICES
A semiconductor device includes a clock gating circuit and a control circuit. The clock gating circuit outputs a gated clock signal based on a clock signal. Transitions of the clock signal are output in the gated clock signal in response to a clock enable signal having an enable value and are disabled from being output in the gated clock signal in response to the clock enable signal having a disable value. The control circuit includes a first portion that operates based on the clock signal. The first portion sets the clock enable signal to the disable value in response to a disable control and sets the clock enable signal to the enable value in response to a wakeup control. The control circuit includes a second portion that operates based on the gated clock signal. The second portion provides the disable control to the first portion during an operation.
Control device, method and equipment for processor
Disclosed in the present application are a control device, method and equipment for a processor. The control device for the processor comprises: an arithmetic circuit and a memory, the arithmetic circuit being connected to the memory. The arithmetic circuit is used to output a control signal according to acquired sensor data, and the control signal is used to control a processor. The control device, method and equipment for the processor according to the present invention may be used to determine whether it is necessary to start the processor according to preset key information, or whether it is necessary to reduce the energy consumption of a processor which is currently in operation, thereby improving endurance.
Controlling accesses to a branch prediction unit for sequences of fetch groups
An electronic device is described that handles control transfer instructions (CTIs) when executing instructions in program code. The electronic device has a processor that includes a branch prediction functional block and a sequential fetch logic functional block. The sequential fetch logic functional block determines, based on a record associated with a CTI, that a specified number of fetch groups of instructions that were previously determined to include no CTIs are to be fetched for execution in sequence following the CTI. When each of the specified number of fetch groups is fetched and prepared for execution, the sequential fetch logic prevents corresponding accesses of the branch prediction functional block for acquiring branch prediction information for instructions in that fetch group.
Multi-functional authentication apparatus and operating method for the same
A multi-functional authentication apparatus and an operation method for the same are provided. The multi-functional authentication apparatus integrates multiple communication modules into one device. A biometric authentication procedure is firstly performed when activating this multi-functional authentication apparatus. A security code is generated through a security authentication mechanism provided by this apparatus after reading biometric features. After that, according to a connection protocol, one of the communication modules of the multi-functional authentication apparatus is activated to connect with an external host. The security code is transmitted to the host via the communication module for identifying a user. The multi-functional authentication apparatus acts as an authenticator that allows a user to login to a computer system or obtain a network service after authentication. The multi-functional authentication apparatus also provides authentication for the user to open an access control device or conduct a mobile payment.
INTEGRATED CIRCUIT, DYNAMIC VOLTAGE AND FREQUENCY SCALING (DVFS) GOVERNOR, AND COMPUTING SYSTEM INCLUDING THE SAME
Disclosed is an integrated circuit, which counts parameters required for a dynamic voltage frequency scaling (DVFS) operation. The integrated circuit includes: an event block accessing a bus, which connects processing devices to each other, and outputting an event signal, based on data transmitted through the bus; a clock counter counting the number of clock signals received from a clock management unit; a plurality of performance counters respectively counting parameters used to calculate a workload, based on the event signal; an interface receiving an operation signal from the DVFS governor, which determines an operation frequency and an operation voltage of a processing device based on the workload, and transmitting the number of clock signals and the parameters to the DVFS governor; and a controller controlling operations of the event block, the clock counter, and the plurality of performance counters, based on the operation signal.
System, apparatus and method for adaptive operating voltage in a field programmable gate array (FPGA)
In one embodiment, a field programmable gate array (FPGA) includes: at least one programmable logic circuit to execute a function programmed with a bitstream; a self-test circuit to execute a self-test at a first voltage, the self-test and the first voltage programmed with first metadata associated with the bitstream, the self-test including at least one critical path length of the function; and a power controller to identify an operating voltage for the at least one programmable logic circuit based at least in part on the execution of the self-test at the first voltage.
System and method for Information Handling System (IHS) optimization using core stall management technology
Embodiments of a system, method, and memory storage device for managing performance optimization of applications executed by an Information Handling System (IHS) are described. In an illustrative, non-limiting embodiment, an IHS may include computer-executable instructions to receive telemetry data associated with an operating behavior of the IHS. Using the telemetry data, the IHS generates a profile recommendation from the received telemetry data using a machine learning (ML) service, and adjusts a core stall management mechanism of a second processor to optimize a performance of the IHS. The second processor performs at least a portion of the operating behavior of the IHS.