In one embodiment, a system on a chip integrated circuit (SoC) is provided that includes graphics processing resources including one or more graphics processing cores a memory subsystem including a memory controller, a physical interface, and a memory device and circuitry to dynamically adjust a voltage and frequency of the memory subsystem based on a workload executed by the graphics processing resources.

Methods and apparatus for optimizing device power and efficiency based on host-controlled hints prior to low-power entry for PCI Express blocks and components. Data structures containing low-power state capability information mapping one or more fine-grained low-power states for each of at least one of an L0s, L1, L1.1, and L1.2 PCIe-defined low-power state are stored on a PCIe device coupled to a Host via a PCIe link. Messages are exchanged over the PCIe link between the Host and PCIe device to configure, using the low-power state capability information, blocks and/or components on the PCIe device to enter a fine-grained low-power state instead of an associated PCIe-defined low-power state mapped to the fine-grained low-power state when the PCIe device detects a power-change event or receives a command to enter the associated PCIe-defined low-power state. Sequences of power-level changes between multiple fine-grained low-power states may also be implemented.

Power consumption is reduced. A semiconductor device includes a sensor circuit including a sensor element, a power management unit, and an arithmetic processing circuit. The power management unit has a function of controlling power supply to the arithmetic processing circuit. The arithmetic processing circuit includes a first circuit including a first storage circuit and a second circuit including a second storage circuit. The first circuit has a function of retaining first data in the first storage circuit during a period where electric power is supplied to the arithmetic processing circuit. The second circuit has a function of reading out the first data retained in the first storage circuit and writing the first data to the second storage circuit during a period where electric power is supplied to the arithmetic processing circuit, and a function of retaining the first data in the second storage circuit during a period where power supply to the arithmetic processing circuit is stopped. The sensor circuit has a function of judging a sensed signal of the sensor element and supplying second data to the power management unit in accordance with the judgment result. The power management unit has a function of restarting or stopping power supply to the arithmetic processing circuit in accordance with the second data.

Examples are disclosed relating to arming and managing power consumption of a haptic feedback component in a stylus prior to actuating the haptic feedback component to produce haptic output. In one example, at least on condition of detecting a first user interaction with the stylus, power is transmitted for at least a first time period to a haptic circuit communicatively coupled to the haptic feedback component. At least on condition of determining that the first time period expires, it is determined if a second user interaction with the stylus is detected. If the second user interaction is detected, the stylus continues transmitting power to the haptic circuit. If the second user interaction is not detected, the stylus ceases transmitting power to the haptic circuit.

Examples are disclosed that relate to allocating power to peripheral device interfaces. One example provides, at a computing device, a method, comprising obtaining a measurement of power consumption by one or more peripheral devices, and based at least on the measurement and on a maximum power tolerance of a power source, allocating to each respective interface a minimum portion of power output from the power source. The method further comprises rendering a remainder of the maximum power tolerance available for consumption by one or more processors, the remainder including the maximum power tolerance minus a sum of the minimum portions, where the remainder and a system portion of power output are available for consumption by the one or more processors, and where a performance attribute of the one or more processors is not throttled while total power consumption does not exceed a threshold power output from the power source.

A Rugged portable device comprises: a base, a cover pivotally connected to the base, a first antenna unit, a second antenna unit, and a control unit. The first antenna unit and the second antenna unit are respectively disposed at an edge of the cover and an edge of the base, and the first antenna unit and the second antenna unit respectively have a near-field antenna and a far-field antenna. When the cover pivots relative to the base and is close to the base, the near-field antenna disposed at the cover and the near-field antenna disposed at the base generate a near-field communication (NFC) sensing signal and the near-field communication sensing signal is transmitted to the control unit. Therefore, the control unit sets up one of functions in the rugged portable device. For instance, the control unit switches off and/or switches on the far-field antenna or a peripheral unit (a keyboard or a camera).

A power management arrangement (10) for a device connection system 5 is described. The power management arrangement comprises a processing module (30) connected to data communication lines (35) for exchanging data with one or more peripherals (100), an interrupt interface (20) connected to interrupt channels (25) for sending an interrupt to and from one or more of the peripherals (100), and a local storage (50) connected to the processing module (30) for storing of logic operations relating to communication with and operation of the plurality of peripherals (100).

A system and method for conservation of battery power in a portable medical device is provided. In one example, a processor arrangement includes a dual core processor having an ARM core and a DSP core. The portable medical device includes a monitor having the dual core processor, in communication with a belt node processor. The DSP core receives physiological data from the physiological sensor and sends the physiological data to the ARM core. The ARM core analyzes the physiological data to determine if a treatment sequence is necessary. The DSP core receives physiological data from the at least one physiological sensor and sends the physiological data to the ARM core, and also analyzes the physiological data to determine proper timing of the treatment sequence by the at least one therapy delivery device to synchronize at least one pulse of the treatment sequence with the physiological data.

A pin control method and device are provided. The method may be applied to a first chip and the first chip includes: a sleep pin connected with a wakeup pin on a second chip, a Request To Send (RTS) pin connected with a Clear To Send (CTS) pin on the second chip, a Receive Data (RXD) pin connected with a Transmit Data (TXD) pin on the second chip. The method includes: receiving, by the sleep pin, a data sending signal sent by the second chip; setting the RTS pin into an effective state according to the data sending signal; receiving, by the RXD pin, data sent by the second chip, the RXD pin being in the effective state when the RTS pin is in the effective state; receiving, by the sleep pin, a transmission completion signal sent by the second chip; setting the RTS pin into an ineffective state according to the transmission completion signal; and determining, according to a current running condition, whether to enter a sleep state.

A microcontroller that can be configured to selectively operate in a synchronous mode or an asynchronous mode, and a method of selectively switching the operating mode is described. The microcontroller can include a processor and a system controller. The processor can be configured to operate synchronously in a synchronous operating mode and asynchronously in an asynchronous operating mode. The processor can also be configured to generate a processor idle status signal indicative of the processor operating in a reduced power mode, and generate a programming signal. The system controller can be configured to generate an asynchronous mode signal based on the programming signal and the processor idle status signal, and provide the asynchronous mode signal to the processor to control the processor to selectively operate in the synchronous operating mode and in the asynchronous operating mode.