Methods and apparatus to implement always-on context sensor hubs for processing multiple different types of data inputs are disclosed. An examples apparatus includes a first processor core to implement a host controller, and a second processor core to implement an offload engine. The host controller includes first logic to process sensor data associated with an electronic device when the electronic device is in a low power mode. The host controller is to offload a computational task associated with the sensor data to the offload engine. The offload engine includes second logic to execute the computational task.

Methods and apparatus to implement always-on context sensor hubs for processing multiple different types of data inputs are disclosed. An examples apparatus includes a first processor core to implement a host controller, and a second processor core to implement an offload engine. The host controller includes first logic to process sensor data associated with an electronic device when the electronic device is in a low power mode. The host controller is to offload a computational task associated with the sensor data to the offload engine. The offload engine includes second logic to execute the computational task.

An information processing device that includes: a memory; and a monitoring processor that is coupled to the memory, wherein the monitoring processor is configured to, in accordance with temperature information of a chip on which a plurality of monitored processors are mounted, stop execution of tasks designated as having low degrees of priority that are set in advance, among a plurality of tasks that are respectively executed at any of the plurality of monitored processors.

An information processing device that includes: a memory; and a monitoring processor that is coupled to the memory, wherein the monitoring processor is configured to, in accordance with temperature information of a chip on which a plurality of monitored processors are mounted, stop execution of tasks designated as having low degrees of priority that are set in advance, among a plurality of tasks that are respectively executed at any of the plurality of monitored processors.

Technologies are disclosed for temporarily hiding user interface (“UI”) elements, such as application windows or tabs. A request can be received to hide a UI element for a specified period of time. When such a request is received, the UI element is hidden and an identifier corresponding to the UI element is moved from a first area of a taskbar to a second area of the taskbar. The application presenting the UI element can be configured for reduced consumption of computing resources while the UI element is hidden. Additionally, notifications associated with the UI element can be disabled while the UI element is hidden. When the specified period of time to hide the UI element has elapsed, the UI element is once again displayed. Additionally, the identifier corresponding to the UI element is moved from the second area of the taskbar back to the first area of the taskbar.

Methods, apparatus, systems, and articles of manufacture are disclosed that prevent heat pipe dryout. An example apparatus includes processor circuitry to at least one of instantiate or execute machine readable instructions to: determine if a temperature of a heat pipe of an electronic device is below a first threshold temperature; cause a program to switch from a first operating mode to a second operating mode when the temperature is below the first threshold temperature, the second operating mode to use more processor circuitry bandwidth than the first operating mode; determine at least one of (1) an occurrence of an increase in a power level of the electronic device or (2) the temperature of the heat pipe satisfies a second threshold temperature; and cause the program to switch from the second operating mode to the first operating mode based on at least one of (1) the occurrence of the increase in the power level or (2) the temperature of the heat pipe satisfying the second threshold temperature.

Examples described herein relate to determination of per-virtualized execution environment power usage based on an identifier of a processor that executes at least two virtualized execution environments, power usage of the processor, and number of virtualized execution environments executed by the processor.

Systems and methods are provided for reducing power consumption of a multi-die device, such as a network processor FPGA (npFPGA). The multi-die device may include hardware resources such as FPGA dies, which may be coupled to NIC dies and/or memory dies. Power consumption of the multi-die device may be reduced by monitoring usage of hardware resources in the multi-die device, identifying hardware resources that are not in use, and gating power to the identified hardware resources. The status of processing elements (PEs) in the multi-die device may be tracked in a PE state table. Based on the PE state table, tasks from a task queue may be assigned to one or more processing elements.

Systems and methods are provided for reducing power consumption of a multi-die device, such as a network processor FPGA (npFPGA). The multi-die device may include hardware resources such as FPGA dies, which may be coupled to NIC dies and/or memory dies. Power consumption of the multi-die device may be reduced by monitoring usage of hardware resources in the multi-die device, identifying hardware resources that are not in use, and gating power to the identified hardware resources. The status of processing elements (PEs) in the multi-die device may be tracked in a PE state table. Based on the PE state table, tasks from a task queue may be assigned to one or more processing elements.

Aspects of the disclosure include methods, systems, and apparatus, including computer-readable storage media for multi-mode integrated circuits with balanced energy consumption. A method includes determining, by one or more processors and based at least on a maximum energy threshold for planned multi-mode system having one or more processing units, a respective number of operations that can be performed per clock cycle by the processing units for each operating mode. The system is configured to consume the same amount of energy per clock cycle in each operating mode, but perform more operations in operating modes corresponding to operations performed on smaller bit-width operands.