A memory device may include a pin for communicating feedback regarding a supply voltage to a power management component, such as a power management integrated circuit (PMIC). The memory device may bias the pin to a first voltage indicating that a supply voltage is within a target range. The memory device may subsequently determine that a supply voltage is outside the target range and transition the voltage at the pin from the first voltage to a second voltage indicating that the supply voltage is outside the target range. The memory device may select the second voltage based on whether the supply voltage is above or below the target range.

Methods, systems, and apparatus, for performing low-power vision sensing. One computing device includes a vision sensor configured to generate vision sensor data and an ambient computing system configured to repeatedly process the vision sensor data generated by the vision sensor according to a low-power detection process. If a detection is indicated by the low-power detection process, the ambient computing system wakes one or more other components of the computing device to perform a high-power detection process using the vision sensor data.

Methods, systems, and apparatus, for performing low-power vision sensing. One computing device includes a vision sensor configured to generate vision sensor data and an ambient computing system configured to repeatedly process the vision sensor data generated by the vision sensor according to a low-power detection process. If a detection is indicated by the low-power detection process, the ambient computing system wakes one or more other components of the computing device to perform a high-power detection process using the vision sensor data.

Systems and methods increase computational efficiency in machine learning accelerators. In embodiments, this is accomplished by evaluating, partitioning, and selecting computational resources to uniquely process, accumulate, and store data based on the type of the data and configuration parameters that are used to process the data. Various embodiments, take advantage of the zeroing feature of a Built-In Self-Test (BIST) controller to cause a BIST circuit to create a known state for a hardware accelerator, e.g., during a startup and/or wakeup phase, thereby, reducing data movements and transitions to save both time and energy.

Systems and methods increase computational efficiency in machine learning accelerators. In embodiments, this is accomplished by evaluating, partitioning, and selecting computational resources to uniquely process, accumulate, and store data based on the type of the data and configuration parameters that are used to process the data. Various embodiments, take advantage of the zeroing feature of a Built-In Self-Test (BIST) controller to cause a BIST circuit to create a known state for a hardware accelerator, e.g., during a startup and/or wakeup phase, thereby, reducing data movements and transitions to save both time and energy.

A task processor has a low power connectivity processor and a high performance applications processor. Software processes have a component operative on a connectivity processor and a component operative on an applications processor. The low power connectivity processor is coupled to a low power front end for wireless packets and the high performance applications processor is coupled to a high performance front end. A power controller is coupled to the low power front end and enables the applications processor and high performance front end when wireless packets which require greater processing capacity are received, and removes power from the applications processor and high performance front end at other times.

A ramp assembly is provided comprising a ramp that is pivotally movable between a fold-in position and a fold-out position through a neutral position, a drive shaft spaced from an axis of pivot of the ramp in a direction perpendicular to the axis, a drive element transmitting rotational force from the drive shaft to the ramp such that rotation of the drive shaft causes movement of the ramp between the fold-in and fold-out positions, and a spring generating a biasing force by being rotationally tensioned, the spring biasing the drive shaft such that the ramp is biased toward the neutral position when the ramp is in the fold-out position and biased toward the neutral position when the ramp is in the fold-in position. A vehicle incorporating such ramp assembly is also contemplated.

Provided are a control and apparatus for a wearable device, an electronic device, and a computer-readable storage medium. The wearable device has a first operation mode and a second operation mode. The first operation mode is a mode for running a first system and a second system. The second operation mode is a mode for running only the second system. The first operation mode has a higher power consumption than the second operation mode. The control method includes: obtaining user behavior data (102), determining a user behavior status based on the user behavior data (104), and switching, in response to detecting that the user behavior status is a sleep status, the wearable device from the first operation mode to the second operation mode (106).

Disclosed in the present application are a control device, method and equipment for a processor. The control device for the processor comprises: an arithmetic circuit and a memory, the arithmetic circuit being connected to the memory. The arithmetic circuit is used to output a control signal according to acquired sensor data, and the control signal is used to control a processor. The control device, method and equipment for the processor according to the present invention may be used to determine whether it is necessary to start the processor according to preset key information, or whether it is necessary to reduce the energy consumption of a processor which is currently in operation, thereby improving endurance.

Various embodiments illustrated herein disclose a computing device comprising a wake-up detect circuit configured to detect a state change of a link light emitting diode (LED) associated with the computing device. The wake-up detect circuit is configured to transmit a wakeup trigger signal to a processor to transit from a sleep mode to a wake-up mode in response to the detection of the state change of the link LED. The processor is configured to establish a connection between the computing device and another computing device via a communication link in the wake-up mode, the other computing device corresponds to a device that has caused the state change of the link LED.