An electronic device is provided. The electronic device operates in a normal mode or a low power mode and includes a first non-volatile memory (NVM), a second NVM configured to store first security data generated in the low power mode, and a security processor configured to access the first NVM to store the first security data in the first NVM in the normal mode.

A method, system, and apparatus determines that one or more tasks should be relocated from a first processor to a second processor by comparing performance metrics to associated thresholds or by using other indications. To relocate the one or more tasks from the first processor to the second processor, the first processor is stalled and state information from the first processor is copied to the second processor. The second processor uses the state information and then services incoming tasks instead of the first processor.

Touch display device and power supply control method are provided. The touch display device includes power supply module including: power supply control circuit; power management chip provides touch operation processing circuit, touch display control driver circuit and touch integrated circuit with operating voltage; the touch operation processing circuit provides first control signal to control signal output terminal when the touch display device is in sleep-state, to enable the power supply control circuit to supply power to the power management chip via second power supply terminal under control of the first control signal; and provides second control signal to the control signal output terminal when the touch display device is in the sleep-state and the touch display panel is touched, to enable the power supply control circuit to supply power to the power management chip via first power supply terminal under control of the second control signal.

In an embodiment, a system may include a plurality of component circuits. The plurality of component circuits may include rate control circuits the control power consumption in the component circuits based on indications of power allocated to the component circuits. In an embodiment, the rate control circuits may transmit power requests for the component circuits and a floor request representing a minimum amount of power that may ensure reliable operation.

Techniques of power management in devices having multi-processor core are described herein. In an example, an ethernet controller of a device comprises a MAC layer module which receives a data packet through a physical network. A multi-processor core coupled to the ethernet controller comprises a first and a second processor. The first and second processor comprise a first driver and a second driver, respectively. The second driver determines that the first processor has entered a power saving mode, receives the data packets directed towards the multi-processor core from the MAC layer module and stores the data packet in a data structure. The econd driver invokes the first driver based on a determination that the data packet is to be handled by the first processor and provides an address of the data structure storing the data packet to the first driver, the data structure being accessible to the first driver.

Techniques of power management in devices having multi-processor core are described herein. In an example, an ethernet controller of a device comprises a MAC layer module which receives a data packet through a physical network. A multi-processor core coupled to the ethernet controller comprises a first and a second processor. The first and second processor comprise a first driver and a second driver, respectively. The second driver determines that the first processor has entered a power saving mode, receives the data packets directed towards the multi-processor core from the MAC layer module and stores the data packet in a data structure. The econd driver invokes the first driver based on a determination that the data packet is to be handled by the first processor and provides an address of the data structure storing the data packet to the first driver, the data structure being accessible to the first driver.

Various embodiments include methods and devices for cache memory power control. Some embodiments may include determining whether a processor is entering a lowest power mode of the processor, and switching a lowest power mode switch control signal to indicate to a cache power switch of the processor switching an electrical connection of a cache memory from a memory power rail to a processor power rail in response to determining that the processor is entering a lowest power mode.

Various embodiments include methods and devices for cache memory power control. Some embodiments may include determining whether a processor is entering a lowest power mode of the processor, and switching a lowest power mode switch control signal to indicate to a cache power switch of the processor switching an electrical connection of a cache memory from a memory power rail to a processor power rail in response to determining that the processor is entering a lowest power mode.

Provided are a communication system, a communication device, and a power saving method, which enable a communication partner device to reliably recognize a communication unit switched to an ON state in response to reception of a predetermined signal from the communication partner device. A BLE chip transmits a BLE BD address when a BT3 chip is in an OFF state. A mobile terminal identifies a BT3 BD address associated with the BLE BD address received from a BLE chip based on stored correspondence data. A card reader switches the state of the BT3 chip to an ON state when the BLE chip receives a predetermined signal transmitted from the mobile terminal. The BT3 chip switched to an ON state starts to communicate data to be used for predetermined information processing to and from the mobile terminal.

A vehicle includes a first controller that sends a request to enter a lower power mode, and a plurality of second controllers. The second controllers each periodically send the first controller signals indicating operation in a normal power mode while being powered by a primary power converter, and responsive to receiving the request, do not send the signals during the low power mode while being capable of powered by an auxiliary power converter that has a maximum power limit less than the primary power converter. Also, the first controller, responsive to not receiving the signals for a predetermined period of time, disconnects the first and second controllers from the primary power converter.