An ultrasound imaging system includes a processor that is programmed to operate the system in a normal operating state and two or more lesser power states. The processor lowers the operating power state to a lesser power state upon detecting one or more operating conditions such as no tissue been imaged in a predetermined time limit or that the imaging system or transducer has not been moved in a time limit. Upon awakening from a power off state, the processor implements a lesser power state before operating at the normal operating state to avoid undue power use until the transducer is positioned to image tissue.

The various embodiments disclose an electronic device including: a storage including a non-volatile memory having a buffer space and a storage space, a storage device controller, and a storage interface, and a processor. According to various embodiments, the processor may be configured to perform control to determine whether the storage supports a high speed data storage mode using a buffer space of a non-volatile memory of the storage, activate a function of writing data buffered in the buffer space of the non-volatile memory into a storage space of the non-volatile memory based on the storage interface operating in a first state based on the storage supporting the high speed data storage mode, and transition the storage interface of the storage to the first state based on no request to the storage being generated during a predetermined time period based on the storage interface operating in a second state.

The various embodiments disclose an electronic device including: a storage including a non-volatile memory having a buffer space and a storage space, a storage device controller, and a storage interface, and a processor. According to various embodiments, the processor may be configured to perform control to determine whether the storage supports a high speed data storage mode using a buffer space of a non-volatile memory of the storage, activate a function of writing data buffered in the buffer space of the non-volatile memory into a storage space of the non-volatile memory based on the storage interface operating in a first state based on the storage supporting the high speed data storage mode, and transition the storage interface of the storage to the first state based on no request to the storage being generated during a predetermined time period based on the storage interface operating in a second state.

A performance management scheme for a processor based on leakage current measurement in field. The scheme performs the operations of detection and correction. The operation of detection measures per core leakage current in the field (e.g., using voltage regulator electrical current counters). The operation of correction changes the processor power management behavior. For example, processor cores showing high leakage degradation may be logically swapped with cores showing low leakage degradation.

A system includes a power profile engine, a power measurement engine, and a power throttling signal generator. The power profile engine receives a desired power profile, e.g., a first profile current average associated with a first time duration and a second profile current average associated with a second time duration. The power measurement engine measures current being drawn and generates a first running average for the measured currents for the first time duration and generates a second running average for the measured currents for the second time duration. The power throttling signal generator generates a first power throttling signal to throttle power in response to the first running average for the measured currents being greater than the first profile current average and generates a second power throttling signal to throttle power in response to the second running average for the measured currents being greater than the second profile current average.

Systems, apparatuses, and methods for saving power on a bus interface are described. A system includes a host, a device, and a repeater interposed between the host and the device. While the host and device are in a low-power state, the repeater monitors a first bus to determine if the device has woken up. When the repeater detects a remote wake-up event initiated by the device, the repeater generates an interrupt which is sent to the host. The host responds to the interrupt by initiating a resume wake-up event procedure that assumes the device is still asleep. In this way, the host is able to stay in the low-power state longer while also using a wake-up procedure that does not require the host to be aware of the existence of the repeater.

Systems, apparatuses, and methods for saving power on a bus interface are described. A system includes a host, a device, and a repeater interposed between the host and the device. While the host and device are in a low-power state, the repeater monitors a first bus to determine if the device has woken up. When the repeater detects a remote wake-up event initiated by the device, the repeater generates an interrupt which is sent to the host. The host responds to the interrupt by initiating a resume wake-up event procedure that assumes the device is still asleep. In this way, the host is able to stay in the low-power state longer while also using a wake-up procedure that does not require the host to be aware of the existence of the repeater.

Systems and methods are disclosed for processor power management using instruction throttling. For example, an integrated circuit may include a processor core including a processor pipeline configured to execute instructions; a register configured to store a power dial value that indicates a portion of available clock cycles for throttling of instruction flow through the processor pipeline; and an instruction throttling circuit configured to periodically stall removal of instructions from a queue in the processor pipeline for a number of clock cycles that is determined based on the power dial value.

Systems and methods are disclosed for processor power management using instruction throttling. For example, an integrated circuit may include a processor core including a processor pipeline configured to execute instructions; a register configured to store a power dial value that indicates a portion of available clock cycles for throttling of instruction flow through the processor pipeline; and an instruction throttling circuit configured to periodically stall removal of instructions from a queue in the processor pipeline for a number of clock cycles that is determined based on the power dial value.

Devices and methods for linear addressing are provided. A device is provided which comprises a plurality of components having assigned registers used to store data to execute a program and a power management controller, in communication with the components. The power management controller is configured to send one of a request to remove power to the components and a request to reduce power to the components when it is determined that the components are idle, execute a first process of one of removing power and reducing power to the components and entering a reduced power state when an acknowledgement of the request is received and execute a second process of restoring power to the components when one or more of the components are indicated to be active.