A circuitry includes a multi-mode switching multiplexer, a control circuit and a receiver. The multi-mode switching multiplexer is arranged to receive multiple mode settings, and select one of the multiple mode settings as an output mode setting. The control circuit is arranged to generate a mode switching signal to control the multi-mode switching multiplexer. The receiver is arranged to set its internal components according to the output mode setting.

An apparatus comprising a power supply, which has first and second components, and actuarial circuitry in communication with the power supply. The actuarial circuitry forecasts the power supply's life expectancy based on real-time measurements of operational parameters of said first and second components.

An apparatus comprising a power supply, which has first and second components, and actuarial circuitry in communication with the power supply. The actuarial circuitry forecasts the power supply's life expectancy based on real-time measurements of operational parameters of said first and second components.

A system for computing devices includes a central processing unit (CPU that is configured to perform in a plurality of power modes, each power mode being pre-defined to have a different code-execution performance capability than remaining ones of the plurality of power modes. The system further includes a sampling peripheral, an electrical output, and a memory device. The memory device is configured to select and execute a specific module from the plurality of modules based on the context-identifying input triggering the specific module. If triggered, each module is executed to receive the context-identifying input from the sampling peripheral, and to operate the CPU in a dedicated power mode of the plurality of power modes.

A system for computing devices includes a central processing unit (CPU that is configured to perform in a plurality of power modes, each power mode being pre-defined to have a different code-execution performance capability than remaining ones of the plurality of power modes. The system further includes a sampling peripheral, an electrical output, and a memory device. The memory device is configured to select and execute a specific module from the plurality of modules based on the context-identifying input triggering the specific module. If triggered, each module is executed to receive the context-identifying input from the sampling peripheral, and to operate the CPU in a dedicated power mode of the plurality of power modes.

Microelectronic circuit com-prises a plurality of logic units and register circuits, arranged into a plu-rality of processing paths, and a plu-rality of monitoring units associated with respective ones of said processing paths. Each of said monitoring units is configured to produce an observation signal as a response to anomalous opera-tion of the respective processing path. Each of said plurality of logic units belongs to one of a plurality of delay classes according to an amount of delay that it is likely to generate. Said de-lay classes comprise first, second, and third classes, of which the first class covers logic units that are likely to generate longest delays, the second class covers logic units that are likely to generate shorter delays than said first class, and the third class covers logic units that are likely to generate shorter delays than said second class. At least some of said plurality of pro-cessing paths comprise logic units be-longing to said second class but are without monitoring units. At least some of said plurality of processing paths comprise logic units belonging to said third class but have monitoring units associated with them.

In one embodiment, a processor includes a power controller having a resource allocation circuit. The resource allocation circuit may: receive a power budget for a first core and at least one second core and scale the power budget based at least in part on at least one energy performance preference value to determine a scaled power budget; determine a first maximum operating point for the first core and a second maximum operating point for the at least one second core based at least in part on the scaled power budget; determine a first efficiency value for the first core based at least in part on the first maximum operating point for the first core and a second efficiency value for the at least one second core based at least in part on the second maximum operating point for the at least one second core; and report a hardware state change to an operating system scheduler based on the first efficiency value and the second efficiency value. Other embodiments are described and claimed.

In one embodiment, a processor includes a power controller having a resource allocation circuit. The resource allocation circuit may: receive a power budget for a first core and at least one second core and scale the power budget based at least in part on at least one energy performance preference value to determine a scaled power budget; determine a first maximum operating point for the first core and a second maximum operating point for the at least one second core based at least in part on the scaled power budget; determine a first efficiency value for the first core based at least in part on the first maximum operating point for the first core and a second efficiency value for the at least one second core based at least in part on the second maximum operating point for the at least one second core; and report a hardware state change to an operating system scheduler based on the first efficiency value and the second efficiency value. Other embodiments are described and claimed.

Examples are disclosed that relate to allocating power to peripheral device interfaces. One example provides, at a computing device, a method, comprising obtaining a measurement of power consumption by one or more peripheral devices, and based at least on the measurement and on a maximum power tolerance of a power source, allocating to each respective interface a minimum portion of power output from the power source. The method further comprises rendering a remainder of the maximum power tolerance available for consumption by one or more processors, the remainder including the maximum power tolerance minus a sum of the minimum portions, where the remainder and a system portion of power output are available for consumption by the one or more processors, and where a performance attribute of the one or more processors is not throttled while total power consumption does not exceed a threshold power output from the power source.

A power supply control unit controls supply and stoppage of power to a plurality of blocks having two or more modules. A clock control unit controls supply and stoppage of clocks to the two or more modules in the plurality of blocks. A first control unit verifies validity of a program stored in a storage unit. A second control unit executes the program determined to be valid as a result of verification by the first control unit. While the program is verified by the first control unit, the power supply control unit supplies power to a block including a module required for the verification, and the clock control unit stops a clock to a module not required for the verification of the block including a module required for the verification.