A local power control arbiter is provided to interface with a global power control unit of a processing platform having a plurality of processing entities. The local power control arbiter controls a local processing unit of the processing platform. The local power arbiter has an interface to receive from the global power control unit, a local performance limit allocated to the local processing unit depending on a global power control evaluation and processing circuitry to determine any change to one or more processing conditions prevailing in the local processing unit on a timescale shorter than a duration for which the local performance limit is applied to the local processing unit by the global power control unit and to select a performance level for the local processing unit depending on both the local performance limit and the determined change, if any, to the prevailing processing conditions on the local processing unit.

The described technology provides a method for dynamically adjusting operating voltage of a device, including receiving device characteristics data related to a device, performing a margining test for the device to generate a performance curve characterizing variation of the device's current performance speeds at various operating voltages from expected performance speeds at the various operating voltages, determining an operating voltage for the device based on the device characteristics data and the performance curve, and adjusting the operating of the device based on the determined operating voltage.

In some examples, an embedded controller of a computing device may detect, when the computing device is in a low-power state, that a smartcard has been connected to a port of the computing device or that data has been received from an input device (e.g., keyboard or biometric input device) connected to the computing device. For the smartcard, the embedded controller may use a card driver to read data stored on the smartcard. The embedded controller may compute a hash value based on the data read from the smartcard or received from the input device. If the hash value matches a previously stored hash value, then the embedded controller may initiate a boot-up process of the computing device. If the hash value does not match the previously stored hash value, then the embedded controller may cause the computing device to remain in the low-power state.

In some examples, an embedded controller of a computing device may detect, when the computing device is in a low-power state, that a smartcard has been connected to a port of the computing device or that data has been received from an input device (e.g., keyboard or biometric input device) connected to the computing device. For the smartcard, the embedded controller may use a card driver to read data stored on the smartcard. The embedded controller may compute a hash value based on the data read from the smartcard or received from the input device. If the hash value matches a previously stored hash value, then the embedded controller may initiate a boot-up process of the computing device. If the hash value does not match the previously stored hash value, then the embedded controller may cause the computing device to remain in the low-power state.

The present invention disclosures a current calibration device for power supply channels in a test system, comprising n power supply channels, n connection switches corresponding to the n power supply channels, m resistors, m selection switches corresponding to the m resistors, a VBIAS power supply, a SPI bus, a host computer and an ammeter, wherein, both n and m are integers greater than 0; one end of each of the n power supply channels is connected to the SPI bus, and another end of each of the n power supply channels is connected to a node Q through a connection switch correspondingly, both ends of the selection switch are connected respectively to the node Q and one end of the resistor, and another end of the resistor is connected to the positive terminal of the ammeter, and the negative terminal of the ammeter is connected to the VBIAS power supply, and the VBIAS power supply is connected to the SPI bus simultaneously. The present invention provides a current calibration device and a current calibration method for power supply channels in a test system, which realizes segmented calibration through a software algorithm and improves measurement accuracy of the power supply channels; and solves a problem that a traditional current calibration for power supply channels can only cover a single point or a few voltage ranges.

The present invention disclosures a current calibration device for power supply channels in a test system, comprising n power supply channels, n connection switches corresponding to the n power supply channels, m resistors, m selection switches corresponding to the m resistors, a VBIAS power supply, a SPI bus, a host computer and an ammeter, wherein, both n and m are integers greater than 0; one end of each of the n power supply channels is connected to the SPI bus, and another end of each of the n power supply channels is connected to a node Q through a connection switch correspondingly, both ends of the selection switch are connected respectively to the node Q and one end of the resistor, and another end of the resistor is connected to the positive terminal of the ammeter, and the negative terminal of the ammeter is connected to the VBIAS power supply, and the VBIAS power supply is connected to the SPI bus simultaneously. The present invention provides a current calibration device and a current calibration method for power supply channels in a test system, which realizes segmented calibration through a software algorithm and improves measurement accuracy of the power supply channels; and solves a problem that a traditional current calibration for power supply channels can only cover a single point or a few voltage ranges.

Various embodiments may include methods and systems for power management of multiple chiplets within a system-on-a-chip (SoC). Various systems may include a power management integrated circuit (PMIC) configured to supply power to a first chiplet and a second chiplet across a shared power rail. The first chiplet may be configured to obtain first sensory information throughout the first chiplet. The second chiplet may be configured to obtain second sensory information throughout the second chiplet, and may be configured to transmit a voltage change message to the first chiplet based on the second sensory information. The first chiplet may be configured to transmit a power rail adjustment message to the PMIC based on the first sensory information and the voltage change message. The PMIC may be configured to adjust the voltage of at least one of the first chiplet and the second chiplet.

Various embodiments may include methods and systems for power management of multiple chiplets within a system-on-a-chip (SoC). Various systems may include a power management integrated circuit (PMIC) configured to supply power to a first chiplet and a second chiplet across a shared power rail. The first chiplet may be configured to obtain first sensory information throughout the first chiplet. The second chiplet may be configured to obtain second sensory information throughout the second chiplet, and may be configured to transmit a voltage change message to the first chiplet based on the second sensory information. The first chiplet may be configured to transmit a power rail adjustment message to the PMIC based on the first sensory information and the voltage change message. The PMIC may be configured to adjust the voltage of at least one of the first chiplet and the second chiplet.

Methods and systems for facilitating improved power consumption control of a plurality of processing cores are disclosed. The methods improve the power consumption control by performing power throttling based on a determined excess power consumption. The methods include the steps of: monitoring using at least one event count component in the respective processing core a plurality of distributed events; calculating an accumulated weighted sum of the distributed events from the event count component; determining an excess power consumption by comparing the accumulated weighted sum with a threshold power value; and adjusting power consumption of the respective processing core based on the determined excess power consumption.

A hardware controller within a core of a processor is described. The hardware controller includes telemetry logic to generate telemetry data that indicates an activity state of the core; core stall detection logic to determine, based on the telemetry data from the telemetry logic, whether the core is in an idle loop state; and a power controller that, in response to the core stall detection logic determining that the core is in the idle loop state, is to decrease a power mode of the core from a first power mode associated with a first set of power settings to a second power mode associated with a second set of power settings.