G06F1/3296

Method and apparatus for saving system power
11580834 · 2023-02-14 · ·

Theft increases the average product cost to consumers. A mentoring system is presented that can help to reduce or prevent the inventory from lost or theft. Theft is a serious concern in the consumer market place. Industry loses billions per year on theft of merchandise. According to a Reuters report, last year, thefts by employees of U.S. retail merchandise accounted for $15.9 billion, or 44 percent of theft losses at stores, more than shoplifting and vendor fraud combined. Thus, the total thief by the customers and store employees during the year 2008 amounted to $36 billion. Several embodiments of ways to control or reduce the thefts in the market place are presented.

Adaptive voltage scaling scanning method and associated electronic device

The present invention discloses an AVS scanning method, wherein the AVS scanning method includes the steps of: mounting a system on chip (SoC) on a printed circuit board (PCB), and connecting the SoC to a storage unit; enabling the SoC to read a boot code from the storage unit, and executing the boot code to perform an AVS scanning operation on the SoC to determine a plurality of target supply voltages respectively corresponding to a plurality of operating frequencies of the SoC to establish an AVS look-up table; and storing the AVS look-up table into the SoC or the storage unit.

Adaptive voltage scaling scanning method and associated electronic device

The present invention discloses an AVS scanning method, wherein the AVS scanning method includes the steps of: mounting a system on chip (SoC) on a printed circuit board (PCB), and connecting the SoC to a storage unit; enabling the SoC to read a boot code from the storage unit, and executing the boot code to perform an AVS scanning operation on the SoC to determine a plurality of target supply voltages respectively corresponding to a plurality of operating frequencies of the SoC to establish an AVS look-up table; and storing the AVS look-up table into the SoC or the storage unit.

Sensing apparatus and sensing system
11579682 · 2023-02-14 · ·

A sensing apparatuses includes a sensor, a processing circuit that acquires sensor output information from the sensor, a communication circuit that transmits transmission information corresponding to the sensor output information, and a clocking circuit that generates time information. The communication circuit receives time information for correction before the processing circuit starts acquiring the sensor output information. The clocking circuit corrects the time information based on the time information for correction received by the communication circuit. The processing circuit starts acquiring the sensor output information based on the corrected time information.

Sensing apparatus and sensing system
11579682 · 2023-02-14 · ·

A sensing apparatuses includes a sensor, a processing circuit that acquires sensor output information from the sensor, a communication circuit that transmits transmission information corresponding to the sensor output information, and a clocking circuit that generates time information. The communication circuit receives time information for correction before the processing circuit starts acquiring the sensor output information. The clocking circuit corrects the time information based on the time information for correction received by the communication circuit. The processing circuit starts acquiring the sensor output information based on the corrected time information.

PROBE FILTER RETENTION BASED LOW POWER STATE
20230039289 · 2023-02-09 · ·

A data fabric routes requests between the plurality of requestors and the plurality of responders. The data fabric includes a crossbar router, a coherent slave controller coupled to the crossbar router, and a probe filter coupled to the coherent slave controller and tracking the state of cached lines of memory. Power state control circuitry operates, responsive to detecting any of a plurality of designated conditions, to cause the probe filter to enter a retention low power state in which a clock signal to the probe filter is gated while power is maintained to the probe filter. Entering the retention low power state is performed when all in-process probe filter lookups are complete.

SYSTEM, METHOD AND NON-TRANSITORY COMPUTER-READABLE MEDIUM FOR CRYPTOCURRENCY MINING
20230037377 · 2023-02-09 ·

A computer may be provided on a mining machine comprising a mother board, a power supply in operable communication with the mother board, an input/output interface in communication with the mother board, and a plurality of hash boards each in communication with the mother board and comprising a plurality of mining chips. The computer may execute instructions that cause the computer to perform establishing communication with an external device, retrieving at least one profit variable from the external device, calculating an estimated profitability of a first mining chip based on the profit variable, and adjusting a chip voltage supplied to the first mining chip and adjusting a chip frequency of the first mining chip to maximize the estimated profitability. Alternatively, the instructions may cause the computer to adjust the chip voltage and the chip frequency to maintain a temperature within a predetermined range.

SYSTEM, METHOD AND NON-TRANSITORY COMPUTER-READABLE MEDIUM FOR CRYPTOCURRENCY MINING
20230037377 · 2023-02-09 ·

A computer may be provided on a mining machine comprising a mother board, a power supply in operable communication with the mother board, an input/output interface in communication with the mother board, and a plurality of hash boards each in communication with the mother board and comprising a plurality of mining chips. The computer may execute instructions that cause the computer to perform establishing communication with an external device, retrieving at least one profit variable from the external device, calculating an estimated profitability of a first mining chip based on the profit variable, and adjusting a chip voltage supplied to the first mining chip and adjusting a chip frequency of the first mining chip to maximize the estimated profitability. Alternatively, the instructions may cause the computer to adjust the chip voltage and the chip frequency to maintain a temperature within a predetermined range.

Buck-Boost Converter
20230045186 · 2023-02-09 ·

A buck-boost power converter is operable in a first mode (step-down) or in a second mode (step-up). The power converter has an inductor, a flying capacitor, a network of six switches and a driver adapted to drive the network of switches with a sequence of states. Depending on the mode of operation the sequence of states comprises at least one of a first state and a second state. In the first state the ground port is coupled to the second port via two paths, a first path comprising the flying capacitor and the inductor, and a second path comprising the flying capacitor while bypassing the inductor. In the second state the first port is coupled to the second port via a path that includes the inductor and the ground port is coupled to the first port via a path that includes the flying capacitor while bypassing the inductor.

High-efficiency low-ripple burst mode for a charge pump

An apparatus is disclosed for operating a charge pump in a high-efficiency low-ripple burst mode. In an example aspect, the apparatus includes a charge pump with a flying capacitor, a switching circuit, and a burst-mode controller. The switching circuit is coupled to the flying capacitor and configured to selectively: be in a burst configuration to charge and discharge the flying capacitor based on a clock signal; or be in a pulse-skipping configuration. The burst-mode controller is coupled to the switching circuit and configured to trigger the switching circuit to transition from the pulse-skipping configuration to the burst configuration at a time that occurs between rising edges of the clock signal. The burst-mode controller is also configured to cause charging of the flying capacitor to occur for approximately half a period of the clock signal responsive to triggering the switching circuit to transition from the pulse-skipping configuration to the burst configuration.